CSE370 Assignment 3

Distributed: 18 January 2005
Due: 25 January 2005

1. Katz/Borriello, Contemporary Logic Design 2e, remainder of Chapter 2 (pp. 47-83)
2. Katz/Borriello, Contemporary Logic Design 2e, Chapter 3, sections 3.1 and 3.2 (pp. 93-114)
   

Exercises:

1. CLD-II, Chapter 2, problem 2.31, parts a and b
2. CLD-II, Chapter 2, problem 2.33, part a.
3. CLD-II, Chapter 2, problem 2.35.
4. CLD-II, Chapter 2, problem 2.45.
5. CLD-II, Chapter 3, problem 3.3, part a,b,c.
6. CLD-II, Chapter 3, problem 3.4, part b.
7. CLD-II, Chapter 3, problem 3.5, part c,d,e (Note: Look closely at part c)
8. 
   

       a) Translate this circuit directly to a Boolean expression that computes the same function.
       b) Express this function as a canonical Sum of Products.
       c) Express this function as a canonical Product of Sums.
       d) Using a K-map, find the minimal Sum of Products expression for this function.
       e) Using a K-map, find the minimal Product of Sums expression for this function.
       f) Draw the circuit corresponding to the minimal Sum of Products representation.

   
   

9. 8.
    

       a) Redraw this circuit using the deMorgan equivalent for gates where appropriate so that the function computed can be read directly from the circuit diagram.
       b) Find the minimal Sum of Products form for this function.
       c) Draw the circuit for this minimal Sum of Products using only NAND gates (and inverters).
       d) Draw the circuit for this minimal Sum of Products using only NOR gates (and inverters).
     
   

Rationale:

• To apply minimization techniques using Karnaugh maps.
• To gain experience minimizing circuits