## CSE370 Assignment 3

### Distributed: 7 April 2006 Due: 14 April 2006

1. Katz/Borriello, Contemporary Logic Design 2e, Chapter 3 pp. 93-114, 139-145.
2. Verilog Reference.

#### Exercises:

1. CLD-II, Chapter 2, problem 2.23
2. CLD-II, Chapter 2, problem 2.25, part b
3. CLD-II, Chapter 2, problem 2.31, part c, d (NOTE: do 2.30 part b only).
4. CLD-II, Chapter 2, problem 2.35.
5. CLD-II, Chapter 2, problem 2.43.
6. CLD-II, Chapter 3, problem 3.3, part c, d.
7. CLD-II, Chapter 3, problem 3.4, part c.
8. CLD-II, Chapter 3, problem 3.5, part b, d.

a) Translate this circuit directly to a Boolean expression that computes the same function.
b) Express this function as a canonical Sum of Products.
c) Express this function as a canonical Product of Sums.
d) Using a K-map, find the minimal Sum of Products expression for this function.
e) Using a K-map, find the minimal Product of Sums expression for this function.
f) Draw the circuit corresponding to the minimal Sum of Products representation.

10.

a) Redraw this circuit using the deMorgan equivalent for gates where appropriate so that the function computed can be read directly from the circuit diagram.
b) Find the minimal Sum of Products form for this function.
c) Draw the circuit for this minimal Sum of Products using only NAND gates (and inverters).
d) Draw the circuit for this minimal Sum of Products using only NOR gates (and inverters).

#### Rationale:

• To apply minimization techniques using Karnaugh maps.
• To gain experience minimizing circuits