CSE370 Assignment 6

Distributed: 29 April 2006
Due: 5 May 2006

Reading:

  1. Katz/Borriello, Contemporary Logic Design 2e, Finish Chapter 6, pp. 307-326

Exercises:

  1. This exercise will give you a chance to deal with an ALU or Arithmetic Logic Unit. As the name suggests, an ALU is the part of the processor that does the actual computations. In the book, section 5.7 covers the design and implementation of a small ALU.  To keep things tractable, you can design a single-bit ALU and then connect up an arbitrary number of these bit-slices to create full-size ALUs.  The goal of this problem is to modify the provided bit-slice to support carry-lookahead addition.

Specifically, you should:

    1. Download this file which contains an archived design with several useful files. To use this design, Open a workspace in Active and select Design->Restore Design and follow the instructions.
    2. Create a single bit ALU that produces the same F output as the one in alu_bit_slice.bde. Instead of generating Cout, your bit-slice should produce P and G outputs suitable for a carry lookahead unit.
    3. Make a 4-bit Alu from 4 of your one-bit ALUs and the carry-lookahead unit from HW5.
    4. Add your 4-bit adder to alu_test.bde and simulate it.

Submit a printout of your bit-slice schematic, and the console input from the successful simulation

  1. CLD-II, Chapter 6, problem 6.10, all parts (use this template).
  2. CLD-II, Chapter 6, problem 6.11, all parts. Include a sentence justifying each of your answers
  3. CLD-II, Chapter 6, problem 6.19.
  4. CLD-II, Chapter 6, problem 6.23.

Rationale:

  • To begin understanding the basic building blocks of sequential circuits.
  • To learn the use of simulation tools and hardware description languages for sequential circuit blocks.
Comments to: cse370-webmaster@cs.washington.edu