In CSE370, we’ll be using Aldec's Active-HDL 7.1 (don’t use this link – it is just informational – use the link below marked “HERE”) as our primary development tool. It includes a schematic editor, a Verilog editor, and an integrated simulator for designs done in any combination of schematics and Verilog. This is particularly useful as we can provide Verilog test fixtures for many of your design that can help you test your implementations. In addition, Active-HDL also provides an interface to synthesis and mapping tools for the programmable logic devices we’ll be using. The synthesis tool we’ll be using is Cypress Semiconductor’s Warp. It will handle all the PLDs we’ll be using in CSE370.
Active-HDL 7.1 and Warp are available outside of the 003 laboratory only for students currently enrolled in CSE370. It utilizes a license server on campus so your machine will require reasonable Internet access when you are using the tool. However, we have a limited number of concurrent licenses for this software. It is EXTREMELY IMPORTANT that if you use Active-HDL at home you completely shut down the applications when you are not actively using it so that the license is released for others to use. If you do not, and we have difficulty getting everyone access to the tool because of this, then we will have to limit home use.
If you understand this usage model and are willing to cooperate in making sure that the most students possible can make effective use of the tool, then you can find download instructions HERE (use this link).
We have developed a set of tutorials to help you make efficient use of the tools. You should find everything you’ll need for CSE370 in the following tutorials (also linked through the appropriate laboratory assignments).
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Tutorial |
Topic |
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ActiveHDL 7.1 Introduction |
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Active-HDL 7.1 Simulations |
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Active-HDL 7.1 Buses and test fixtures |
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Active-HDL 7.1 Verilog |
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PAL Programming |
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How to make a CTL file for PAL Programming |