//-------------------------------------------------------------------------------------------------- // // Title : count_logic // Design : lab6 // Author : cse // Company : uw // //------------------------------------------------------------------------------------------------- // // File : count_logic.v // Generated : Tue Nov 11 18:53:22 2003 // From : interface description file // By : Itf2Vhdl ver. 1.20 // //------------------------------------------------------------------------------------------------- // // Description : // //------------------------------------------------------------------------------------------------- `timescale 1ps / 1ps //{{ Section below this comment is automatically maintained // and may be overwritten //{module {count_logic}} module count_logic (CLK, load, clear, ENP, ENT, rco, value_out, value_in); input CLK ; input load ; input clear ; input ENP ; input ENT ; input [3:0] value_in; output rco; output [3:0] value_out; reg [3:0] counter; assign value_out = counter; assign rco = ENT && (counter == 15); always@(posedge CLK) begin if (clear) // clear // fill in a statement for clearing the counter else if (load) // load // fill in a statement for loading the counter else if (ENP && ENT) // count // fill in a statement for incrementing the counter else // hold // fill in a statement for holding the counter end endmodule