CSE370 Laboratory Assignment 3


Constructing Simple Logic Circuits

Distributed: October 16, 2006
Due: End of lab


In this lab you will learn how to use test fixtures, program in Verilog and apply your minimization skills to realize two circuits to detect a Fibonacci number after you have simulated them in Verilog.  This is a long lab, so get started early! You will  apply your Active-HDL 7.1 skills to construct and verify your Fibonacci detection circuits and use an XOR gate to detect differences between your two circuits. By the end of this lab you should feel comfortable that you can enter a schematic for a design, set up simulation stimuli, and verify that your circuit is correct. After verifying your circuits in simulation you will wire up both of your detection circuits on the prototyping board.


  1. Follow Tutorial #2 and complete part 1, the section on test fixtures.  It is not necessary to do part 2, the 4-bit adder/subtractor at this point.  When you are complete, get your waveform and simulation checked off by a TA.  There is no need to print out the waveform!
  2. Follow Tutorial #3.  Show your Verilog code and simulation to a TA when you have completed the tutorial and test.
  3. Design two circuits to detect a Fibonacci number between 1 and 15 (1, 2, 3, 5, 8, 13). One circuit should consider the number "0" a don't care value while the second circuit should be completed without don't cares (i.e. the number zero should be considered false). Make sure to minimize each circuit by using K-maps. NOTE: You will need to wire up BOTH circuits at the same time on your prototyping board so you should be careful with your gate choice when designing your circuits. Keep this in mind as you may have to change the gates you use as you will be required to use ONLY the gates in your prototyping kit and you only have 1 chip for each gate type with the exception of an inverter chip which you should have two. Link to chips in your kit
  4. Create two Verilog modules in Active-HDL to detect a Fibonacci number between 1 and 15 (1, 2, 3, 5, 8, 13) using both of the methods above.
  5. Next create a test fixture to verify your Fibonacci Verilog modules. Show your code to a TA to get checked off.
  6. Create a schematic in Active-HDL that includes both of your Fibonacci number detection circuits.  Connect the outputs of both your circuits to a XOR gate to detect when the circuits behave differently. Make sure to verify that you have enough gates in your prototyping kit when making the schematic so you can wire up the identical circuit. NOTE: The gates in your Active-HDL solution must exactly match the gates used in your prototyping board solution.
  7. Simulate both of your Fibonacci number detection circuits using the same technique as in the tutorial #1.  Create stimulators for the inputs A, B, C, and D with D changing every 20 time units, C every 40, B every 80, and A every 160.  Make sure to run your simulation long enough so that the inputs take on all possible combinations.  Your simulation results should clearly show that the output of the function is only true when the inputs correspond to a Fibonacci number (1, 2, 3, 5, 8, or 13). Your waveform should display 7 items: the 4 inputs (A, B, C, D),  the output from your XOR gate, and the two "wire/nets" (with_dont_cares/without_dont_cares) that connect each detection circuit to the XOR gate. Please refer to tutorial #1 to review how to name "wires/nets" or setup simulation stimuli.
  8. Using the schematic from task 6, construct both of your circuits that will identify a "Fibonacci Number" on the prototyping board by connecting the inputs to switches and the output of the XOR to an LED. In addition connect the results of the two detection circuits to LEDs. You will need 4 switches and 3 LEDs for this part. Please use: SW1 through SW4 for number value, LED1 for the XOR result, LED2 for the without don't cares result, and LED 3 for the with don't cares result. Demonstrate your circuit to a TA and have them check you off as having completed this laboratory assignment. They may ask you to show them your work and explain your circuit. HINT: If you circuit is not working as expected use the logic probe to trace through the circuit to help you identify any wiring errors


 Lab Demonstration/Turn-in Requirements: A TA will "check you off" after you

  1. Show the simulation from tutorial #2 which demonstrates that your original full adder works.
  2. Show the Verilog code for your one bit full adder and the simulation that proves it is correct.
  3. Show the Verilog code and test fixture for both Fibonacci detection modules.
  4. Show the schematic and simulation of the Fibonacci detection circuits.
  5. Demonstrate your "Fibonacci Number" detection circuit.

NOTE: The gates in your Active-HDL solution must exactly match the gates used in your prototyping board solution.

Comments to: mailto:cse370-webmaster@cs