## CSE370 Assignment 6

### Distributed: 1 November 2006

Due: 8 November 2006

#### Reading:

- Katz/Borriello, Contemporary
Logic Design 2e, Chapter 5 (pp. 221-253).

#### Exercises:

- Construct a 4-bit
ripple-carry adder with four full-adder blocks using Aldec
ActiveHDL. First construct - out of basic gates
from the lib370 library - a single-bit full-adder block to reuse. Verify
your design using simulation, turn in the schematic and timing waveforms
showing what happens when you have "1111" and "0000"
as the numbers to be added and you change the "0000" to
"0001". How long does it take the sum to get to the right value?
Repeat this experiment starting with "1010" and "0000"
and changing the "0000" to "0101". Explain the
differences between the two cases.
- Repeat the previous problem
but now construct a 4-bit carry-lookahead
instead. Use the same full-adder module as the previous problem.
Repeat the two simulations. How much faster is the carry-lookahead adder in both cases? Explain the differences
with the result of the previous problem. How do your circuits from
this problem and the previous one compare in the total number of gates
they use (remember to consider gates in all sub-blocks)?
- CLD-II, Chapter 5, problem
5.4, parts a and b (use a 9-bit binary representation
for the output).
- CLD-II, Chapter 5, problem
5.9, parts a and b.
- CLD-II, Chapter 5, problem
5.10.

#### Rationale:

- To design hierarchical
combinational circuits from high-level specifications.
- To better appreciate the
differences between ripple-carry, carry-lookahead,
and carry-select adders.

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