## CSE370 Assignment 5

### Distributed: 25 October 2006

Due: 1 November 2006

Reading:

- Katz/Borriello, Contemporary Logic
Design 2e, Sections 4.1 and 4.2 (pp. 155-196 – you can skip the material
on FPGAs, although I encourage you to read it for general knowledge about
more current technologies).

#### Exercises:

- CLD-II, Chapter 4, problem
4.7, parts a and b.
- CLD-II, Chapter 4, problem
4.14, parts a and b.
- CLD-II, Chapter 4, problem
4.13.
- CLD-II, Chapter 4, problem
4.18, parts a, b, c, and d. For
parts c and d, use the ROM and PLA on the worksheet
and minimize use of gates in the PLA.
- Use a copy of the worksheet to show how to implement the
following set of functions using a ROM, a PLA and a PAL. That is, use a
ROM to implement all three functions, then a PLA to implement all three,
and finally a PAL. For the PLA, try to reduce the number of AND gates you
use by sharing terms. Make sure to clearly label your solutions.
- f1(a,b,c,d) = Σ
m(0, 4, 9, 11, 15)
- f2(a,b,c,d) = Σ
m(0, 2, 4, 6, 12, 13) + d(8, 9)
- f3(a,b,c,d) = Σ
m(1, 2, 6, 9, 15) + d(5, 8, 13)

#### Rationale:

- To practice realizing
combinational logic using regular logic structures.
- To begin to understand the
process of mapping logic to programmable logic devices.

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