CSE370 Assignment 3

Distributed: 11 October 2006
Due: 18 October 2006

1. Katz/Borriello, Contemporary Logic Design 2e, Sections 3.4.2 through 3.5.4 (pp. 126-133)
2. Katz/Borriello, Contemporary Logic Design 2e, Section 3.6 (pp. 139-147)
3. Katz/Borriello, Contemporary Logic Design 2e, Section 6.1 (pp. 259-282)

Exercises:

1. CLD-II, Chapter 3, problem 3.8, part d.
2. CLD-II, Chapter 3, problem 3.9, part e.
3. CLD-II, Chapter 3, problem 3.15.
4. CLD-II, Chapter 3, problem 3.21, all parts.
5. CLD-II, Chapter 3, problem 3.26, all parts.
6. CLD-II, Chapter 3, problem 3.32 (in behavioral, not structural form).

Rationale:

• To practice basic combinational logic design.
• To demonstrate the timing behavior of a combinational logic circuit.
• To begin the process of using hardware description languages.