`timescale 1ns / 1ns module rs232_tf (clk, reset,displayed,sdata,received); input clk; input reset; input displayed; //flag value to initiate end of handshake output received; output sdata; reg sdata; // holds output to converted from serial to parallel reg received; //flag value initiating handshake reg [3:0] bitCount; // Count of number bits sent reg [7:0] char; reg [2:0] lettercounter; // Keep the state machine from starting until the LCD has // had a chance to reset. Actually, we only need to wait // long enough so that the LCD is finished reseting before the // first write signal reg hold; initial begin hold = 1; #120 hold = 0; //!!!!!WARNING!!!! ASSUMES 10 NS CLOCK CYCLE ADJUST ACCORDINGLY end // Character generator (generates "Good Job" "'h47'h6f'h6f'h64'h4a'h6f'h62") always @(posedge clk) begin if (reset) begin received <= 0; sdata <= 1; char <= 8'h47; lettercounter <= 0; end else if (!received && !displayed) begin // setup state machine received <= 1; bitCount <= 0; sdata <= 0; //output start bit end else if (received && !displayed && (bitCount < 8)) begin // output the next value in the buffer sdata <= char[bitCount]; bitCount <= bitCount + 1; end else if (received && !displayed && (bitCount >= 8)) begin // if done shifting, reset shifting, set done and keep output high sdata <= 1; end else if (received & displayed) begin // reset done once handshake completes in other always block or if nothing is happening received <= 0; // move to next letter case (lettercounter) 0: begin char <= 8'h6f; lettercounter <= lettercounter + 1; end //o 1: begin char <= 8'h6f; lettercounter <= lettercounter + 1; end //o 2: begin char <= 8'h64; lettercounter <= lettercounter + 1; end //d 3: begin char <= 8'h4a; lettercounter <= lettercounter + 1; end //J 4: begin char <= 8'h6f; lettercounter <= lettercounter + 1; end //o 5: begin char <= 8'h62; lettercounter <= lettercounter + 1; end //b 6: begin char <= 8'h47; lettercounter <= 0; end //G endcase end end endmodule