CSE370 Laboratory Assignment 4

Programming in Verilog

Distributed: January 24, 2005
Due: By end of lab session

Objectives

In this laboratory assignment you will continue to learn how to use the Aldec Active-HDL tool. This time the focus will be on how to create Verilog modules.  You will also see how Verilog modules can be used as test fixtures to help you verify your circuit.  By the end of this lab you should feel comfortable creating a Verilog module directly and setting up a test fixture.

Tasks

  1. Complete Part 1 of  the Active-HDL Tutorial#2 that covers test fixtures. Part 1 is very important as you'll be creating and testing many of your own modules over the rest of the quarter. Make sure you spend the time to get comfortable with the process.
  2. Complete the Active-HDL Tutorial #3, which describes how to write simple Verilog modules and use them in schematics. As part of the tutorial, you will write and test the Verilog module for a full-adder. Create a test schematic and using the test fixture from Task 1 make sure that your Verilog module works correctly.
  3. Create a Verilog module in Active-HDL to detect a Fibonacci number between 1 and 15 (1, 2, 3, 5, 8, 13). Next create a test fixture to verify your Fibonacci verilog module. Hand in a print out of both the Verilog module and test fixture.



 Lab Demonstration/Turn-in Requirements: A TA will "check you off" after you:

  1. Hand in the printout of your Fibonacci verilog module and your test fixture from task 3.

Comments to: cse370-webmaster@cs