//------------------------------------------------------------ // // Title : MagReaderBuffer // Design : Test Fixture for mag stripe reader // //------------------------------------------------------------ // // Generate magstripe reader data // //------------------------------------------------------------ `timescale 1 ns / 1 ns module magreader_tf (reset, clk, outRCP, outRDP, outCLS); input reset, clk; output outRCP, outRDP, outCLS; reg outRCP, outCLS, outReset; integer delay = 0; // Generate delays integer count = 0; // Count bits we have sent parameter CLS_STATE = 0; // These specify the delays in terms of clock cycles parameter BEFORECLS = 14, // From reset to CLS asserted AFTERCLS = 25, // From reset to first clock CPHIGH = 1 , CPLOW = 3,// Clock high and low time CLSDONE = 4; // From end of data to CLS off parameter BUFSIZE = 64; // Number of bits sent // Buffer for input data bits reg [BUFSIZE-1:0] data; // RDP output from data buffer assign outRDP = ~data[0]; // States used to generate data parameter CLS = 0, DATA = 1, DONE = 2; reg [1:0] state; always @(posedge clk) begin if (reset) begin // Make sure the low order bits are the sentinel character. // data[0] is the first high bit for initialization data <= 64'b00000_0000001_0000001_0010000_0101100_0101100_0100101_1101000_1000101_000; state <= CLS; // Start by asserting CLS delay <= 0; count <= 0; outCLS <= 1; outRCP <= 1; outReset <= 1; end else begin delay <= delay + 1; case (state) CLS: begin outReset <= 0; if (delay == BEFORECLS) begin outCLS <= 0; end else if (delay == AFTERCLS) begin state <= DATA; delay <= 0; end end DATA: begin if (delay == CPHIGH) begin outRCP <= 0; end else if (delay == (CPHIGH+CPLOW)) begin delay <= 0; outRCP <= 1; count <= count + 1; data <= { 1'b0, data[(BUFSIZE-1):1] };// Shift data right if (count == (BUFSIZE-1)) state <= DONE; end end // case: DATA DONE: begin if (~outCLS && (delay == CLSDONE)) begin outCLS <= 1; end end endcase // case(state) end // else: !if(Reset) end // always @ (posedge clk) endmodule // magreader_tf