– Spring 2005
Introduction to Digital Design
Homework Set 4
DISTRIBUTED: April 20
DUE: April 29, Start of class
Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.
Late Homework Policy:
The weekly assignments are due at the beginning of class. Assignments handed in during or immediately after class will incur a 10% penalty. We will penalize your assignment 10% per day for each additional day late.
Please show all of your work. Your solutions must be legible…we will not spend time trying to decipher poorly written assignments.
This homework assignment will be concerned mostly with designing circuits using Active-HDL, although you will be practicing concepts you have learned in class. By this time, you should have completed all the Active-HDL tutorials. The test fixtures are linked here and are in the course hw4 folder.
1. (30 points) In this problem we will revisit the multiplexor circuit that you have already designed. Recall that this is a function of three inputs, A, B and S: If S=0, then the output=A; if S=1, then the output=B. (We also called it an if-then-else gate.)
a) Find both the minimal SOP and POS circuit implementation of this function.
b) Using Active-HDL, enter the schematics for both these circuits in the
same block diagram. Use the test fixture in the following file to test
your circuits: \\ntdfs\cs\cse\courses\cse370\05sp\hw4\mux_tf.v
Print the waveform from your simulation. Are there glitches in the output of your circuits? Explain what causes them, and explain carefully why the circuits have different behaviors.
c) In a new block diagram, design a single circuit implementation that does not have glitches on the output. Use the same test fixture, and print the waveform from your simulation.
2. (50 points) In this problem, you will implement and test a complete 16-bit carry-lookahead adder using Active-HDL. You will find test fixtures for each of the components and the final circuit in the courses hw4 folder. Make sure you use only components from the lib370 library.
a) Design and test a 1-bit adder which has three inputs, A, B, Cin, and three outputs, Sum, P, and G, where P and G are the propagate and generate functions. You may use either a schematic with gates, or a Verilog file with equations like that in Lab#5.
b) Using your 1-bit adder, design and test a 4-bit adder component which has three input busses, A[3:0], B[3:0], Cin[3:0] and three output busses, Sum[3:0], P[3:0] and G[3:0]. (This 4-bit adder is just four independent copies of the 1-bit adder.) You must use a schematic for this.
c) Design and test a 4-bit carry-lookahead component that has three inputs, P[3:0], G[3:0], Cin, and three outputs, Cout[3:0], BlockP, and BlockG. BlockP and BlockG are the block propagate and block generate functions. You may use either a schematic with gates, or a Verilog file with equations.
d) Using your 4-bit adder component and 4-bit carry-lookahead component, design and test a 16-bit carry-lookahead adder. You must use a schematic for this.
e) What is the size (# of gates) and delay of your 16-bit carry-lookahead adder?
f) If you continued and made a 64-bit carry-lookahead adder using these components, what would be the size and delay of that circuit?