Reading Guide for the CSE 370 Textbook

Randy H. Katz and Gaetano Borriello, "Contemporary Logic Design" Benjamin-Cummings/Addison-Wesley, 2^nd edition

As usual, our textbook covers more material that we can cover in class. Some of the optional material will be covered in CSE467, Advanced Logic Design, while others are supplementary material.  The text also covers some material in a different order than we do in lectures.  For example, we will delay discussing Verilog until pretty late in the quarter - we don't need it until then.
Optional or omitted topics are in GREEN.

Text		Comments
Chapter 1	Optional	This is an overview of the area of digital design.  It will make more sense after you finish the class.
Appendix A + Number Systems	Required	Covers binary numbers, 1's and 2's complement representation, arithmetic on binary numbers, conversions between bases
Chapter 2: p.33-49, 56-76	Required	Boolean Algebra, canonical forms, cubes, K-maps
p.49-56	Required	Circuit delays, hierarchy in circuits, case study
p.76-83	Required	Multi-level logic
Chapter 3: p.93-103, 108-110	Required	2-level logic minimization, K-maps, ESPRESSO algorithm
p.104-108	Omit	Quine-McCluskey method
p.111-114	Required	DeMorgan's law and logic gate equivalents
p.114-126	Omit	Multi-level logic minimization (covered in CSE467)
p.126-137	Required	Circuit timing and Hazards/Glitches (dynamic hazards optional)
p.139-145		Verilog intro (covered 2nd half of class)
Chapter 4: p.153-164	Optional	History of circuit technologies
p.166-182, 184-205	Required	ROMs, PLAs, PALs, decoders , multiplexers.  We are covering this in a different order, but all at the same time as in the book. Discussion of lookup-table based FPGAs (p. 203) is optional.
p.206-208	Required	Tri-state logic
p.209-212	Optional	Case-study, Wired-OR logic
Chapter 5: p.221-234	Optional	Case-studies
p.234-238	Required	Case-studies
p.238-244	Required	Ripple-carry adder, carry-lookahead adder
p.244-252	Optional	BCD adder, Carry-select adder, ALU, multiplier (covered in CSE467)
Chapter 6: p.259-273	Optional**	Details of latches and flip-flops - optional except for RS and master-slave RS flip-flops
p.273-285	Required	Clocking, edge-triggered registers, latches, timing constraints, asynchronous inputs (simplified)
p.285-287	Omit	Self-timed circuits (covered in CSE467)
p.288-294	Required	Registers, shift registers
p.295-299	Optional	Verilog for sequential circuits
Chapter 7: p.307-316	Required	Counters, FSMs
p.316-320	Optional	Catalog counters.  Largely obsolete.
p.321-347	Required	State machine design
Chapter 8: p.355-367	Required	State minimization
p.367-380	Required	State assignment
p.380-392	Optional	State machine partitioning
Chapter 9:	Optional	Sequential Logic Technologies
Chapter 10	Optional	Sequential Logic Case Studies

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