CSE 370
Spring 2005

Course Calendar 

This is the schedule of lectures and related readings, homework due dates, and quiz and exam dates.

You can expect a homework assignment every week. Assignments will typically be handed out on Wednesday in class, and due the following Friday at the beginning of class. We may ask you to submit assignments done using the CAD Tools (Active-HDL) electronically. We will give you instructions on how to do this.

The last column indicates the pages of the textbook that are relevant to the lecture material. I am counting on you to read this twice – once before we cover it in class, and once again to make sure you understand it. The textbook is also a good source of additional explanations and examples.

Guide to reading the text.

 

Week

Day

Date

Topic

Textbook reading

#1

M

3/28

Introduction and Course Overview

pp. 1-9

 

W

3/30

Binary numbers, Boolean algebra
Assignment #1 distributed

Appendix A
pp. 33-36

 

F

4/1

Boolean algebra and theorems, gates 

pp. 37-45

#2

M

4/4

Boolean functions and logic circuits
Example circuits: decoders & multiplexors

pp. 45-56

 

W

4/6

2-level logic, canonical forms
Assignment #2 distributed

pp. 57-66

 

F

4/8

Graphical representations of Boolean functions

Assignment #1 due; Quiz 1

pp. 66-77

#3

M

4/11

Karnaugh Maps/Logic minimization

pp. 66-77

 

W

4/13

2-level logic minimization
no big K-maps or Quine-McCluskey

Assignment #3 distributed

pp. 95-104

 

 

F

4/15

Structured logic implementation: ROMs, PLAs

Assignment #2 due

pp. 170-209

#4

M

4/18

Structured logic implementation: PLAs, PALs

170-209

 

W

4/20

Multi-level logic circuits

Assignment #4 distributed

pp. 77-85

 

F

4/21

Combinational logic delay and glitches
Assignment #3 due;  Quiz 2

pp. 131-140

#5

M

4/25

Ripple-carry adder; carry-lookahead adder

pp. 239-249

 

W

4/27

ALU, multiplier design
Assignment #5 distributed

pp. 249-257

 

F

4/29

Registers

Assignment #4 due

pp. 261-279

#6

M

5/2

Registers and clocking: counters and shift registers

pp. 289-294

 

W

5/4

Sequential circuits: Finite state machines and state diagrams
Assignment #6 distributed

pp. 310-323

Class notes

 

F

5/6

State diagrams/State tables
Assignment #5 due;  Quiz 3

pp. 324-335

Class notes

#7

M

5/9

Verilog for combinational and sequential circuits

Class notes

 

W

5/11

Control/Datapath design
Assignment #7 distributed

Class notes

 

F

5/13

Simple processor design

Assignment #6 due

Class notes

#8

M

5/16

Implementing FSMs

Mealy vs. Moore FSMs

pp. 335-342, Class notes

 

W

5/18

Verilog HDL: combinational logic
Assignment #8 distributed

Class notes

 

F

5/20

Verilog HDL: sequential logic
Assignment #7 due;  Quiz 4

Class notes

#9

M

5/23

Simple processor design

Class notes

 

W

5/25

Simple processor design

Class notes

 

F

5/27

Simple processor design

Class notes

#10

M

5/30

Holiday  

 

 

W

6/1

Non-gate logic: Tristate and open-collector drivers

 

 

F

6/3

Clock skew; asynchronous inputs
Assignment #8 due

Quiz 5

6.2

#11

M  2:30

6/6

Final Exam

 

Other UW Time Schedules

UW Academic Calendar

Autumn 2005 final exam schedule (CSE370 final exam may differ in time)