CSE 370

This is the schedule of lectures and related readings, homework due dates, and quiz and exam dates.
You can expect a homework assignment every week. Assignments will typically be handed out on Wednesday in class, and due the following Friday at the beginning of class. We may ask you to submit assignments done using the CAD Tools (ActiveHDL) electronically. We will give you instructions on how to do this.
The last column indicates the pages of the textbook that are relevant to the lecture material. I am counting on you to read this twice – once before we cover it in class, and once again to make sure you understand it. The textbook is also a good source of additional explanations and examples.


Week 
Day 
Date 
Topic 
Textbook reading 
#1 
M 
3/28 
Introduction and Course Overview 
pp. 19 

W 
3/30 
Binary numbers, Boolean algebra 
Appendix A 

F 
4/1 
Boolean algebra and theorems, gates 
pp. 3745 
#2 
M 
4/4 
Boolean functions and logic circuits 
pp. 4556 

W 
4/6 
2level logic, canonical forms 
pp. 5766 

F 
4/8 
Graphical representations of Boolean functions Assignment #1 due; Quiz 1 
pp. 6677 
#3 
M 
4/11 
Karnaugh Maps/Logic minimization 
pp. 6677 

W 
4/13 
2level logic minimization Assignment #3 distributed 
pp. 95104 

F 
4/15 
Structured logic implementation: ROMs, PLAs Assignment #2 due 
pp. 170209 
#4 
M 
4/18 
Structured logic implementation: PLAs, PALs 
170209 

W 
4/20 
Multilevel logic circuits Assignment #4 distributed 
pp. 7785 

F 
4/21 
Combinational logic delay and glitches 
pp. 131140 
#5 
M 
4/25 
Ripplecarry adder; carrylookahead adder 
pp. 239249 

W 
4/27 
ALU, multiplier design 
pp. 249257 

F 
4/29 
Registers Assignment #4 due 
pp. 261279 
#6 
M 
5/2 
Registers and clocking: counters and shift registers 
pp. 289294 

W 
5/4 
Sequential circuits: Finite state machines and state
diagrams 
pp. 310323 Class notes 

F 
5/6 
State diagrams/State tables 
pp. 324335 Class notes 
#7 
M 
5/9 
Verilog for combinational and sequential circuits 
Class notes 

W 
5/11 
Control/Datapath design 
Class notes 

F 
5/13 
Simple processor design Assignment #6 due 
Class notes 
#8 
M 
5/16 
Implementing FSMs Mealy vs. Moore FSMs 
pp. 335342, Class notes 

W 
5/18 
Verilog HDL: combinational logic 
Class notes 

F 
5/20 
Verilog HDL: sequential logic 
Class notes 
#9 
M 
5/23 
Simple processor design 
Class notes 

W 
5/25 
Simple processor design 
Class notes 

F 
5/27 
Simple processor design 
Class notes 
#10 
M 
5/30 



W 
6/1 
Nongate logic: Tristate and opencollector drivers 


F 
6/3 
Clock skew; asynchronous inputs Quiz 5 
6.2 
#11 
M 
6/6 
Final Exam 

Other UW Time Schedules
Autumn 2005 final exam schedule (CSE370 final exam may differ in time)