Collaboration Policy:

Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.

Late homework cannot be accepted. Homework is due at the beginning of class on the date indicated by the schedule


CLD-II, Chapter 8,Sections 1,2 and 4 (pp. 355-380, 386-391)


  1. CLD-II, Chapter 8, problem 8.2
  2. CLD-II, Chapter 8, problem 8.4
  3. CLD-II, Chapter 8, problem 8.26 all parts except d - just use a sequential state assignment. A test fixture for the Verilog part of the problem is available here. You will need to use the ClockGen part in lib370 to make the test fixture work in sync with your module.

Comments to: (Last Update: 11/18/05 )