Collaboration Policy:

Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.

Late homework cannot be accepted. Homework is due at the beginning of class on the date indicated by the schedule

Problems

  1. CLD-II, Chapter 5, problem 5.12 (ActiveHDL). The goal here is to produce a "bit-slice" corresponding to all the logic needed to compute 1 bit of the result for each operation. By connecting these slices we can build an ALU of arbitrary width. Reuse gates whenever possible! After you have constructed your bitslice, you may test it by wiring 4 together in Ripple-Carry fashion and using this test fixture. Hand in the schematic for your ALU bitslice only
  2. CLD-II, Chapter 6, problem 6.1.
  3. CLD-II, Chapter 6, problem 6.2, don't worry about the type of switch, just use digital inputs and assume that the inputs all go high and stay high at different times. Your circuit should have as many outputs as inputs, but only the output corresponding to the first switch should ever go high. Explain why this is a sequential circuit?
  4. CLD-II, Chapter 6, problem 6.10 (use template).
  5. Read the description in problem 6.24 for a 4-bit shift register. We will extend this design to 8-bits using the '374 component from lib370 in ActiveHDL. Using this base schematic, implement the following: Turn in your completed schematic for the three components above. For those of you who want some way of testing your schematics, a very non-exhaustive test fixture is located here.

Comments to: cse370-webmaster@cs.washington.edu (Last Update: 11/01/05 )