Collaboration Policy:

Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.

Late homework cannot be accepted. Homework is due at the beginning of class on the date indicated by the schedule

Problems

Please show all of your work. Your solutions must be legible…we will not spend time trying to decipher poorly written assignments.

1. Text 4.2, b
2. Text 4.7, b
3. Text 4.10
4. Text 4.14 b
5. The ripple carry design for an adder in Tutorial #2 is effective, but slow because of the long chain of carry gates. A carry-lookahead adder addresses this problem by computing the carry-in for later gates in parallel with the sums. In this problem you will construct a 16-bit carry-lookahead adder.

   a) Design and test a 1-bit adder that has 3 inputs, A, B, Cin and three outputs: Sum, P, and G. P and G are the propogate and generate functions accordingly, and are defined in the following way: G = AB, P = A xor B. You may do this either with Verilog or a schematic

   b) Using your 1-bit adder, design and test a 4-bit adder component which has three input busses, A[3:0], B[3:0], Cin[3:0] and three output busses, Sum[3:0], P[3:0] and G[3:0]. (This 4-bit adder is just four independent copies of the 1-bit adder.) You must use a schematic for this.

   c) Design and test a 4-bit carry-lookahead component that has three inputs, P[3:0], G[3:0], Cin, and three outputs, Cout[3:0], BlockP, and BlockG. BlockP and BlockG are the block propagate and block generate functions. You must use a schematic for this.

   d) Using your 4-bit adder component and 4-bit carry-lookahead component, design and test a 16-bit carry-lookahead adder. You must use a schematic for this.

   e) What is the size (# of gates) and delay of your 16-bit carry-lookahead adder?

   f) If you continued and made a 64-bit carry-lookahead adder using these components, what would be the size and delay of that circuit?

   Turn-in your implementations/console outputs for part c,d and the answers to part e,f.

6. These are some short exercises involving binary and decimal numbers:
   
   a) Convert the following numbers to 8-bit binary numbers using a two's complement system:
   114
   -37
   
   b) Convert the following 8-bit two's complement signed binary numbers to decimal:
   11010100
   00110101
   
   c) How can you detect if a two's complement binary addition or subtraction operation has overflowed?