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CSE 370: Autumn 2005 |
Course Calendar
This is the schedule of lectures and related readings, homework due dates, and quiz and exam dates.
You can expect a homework assignment every week. Assignments will typically be handed out on Wednesday in class, and due the following Friday at the beginning of class. We may ask you to submit assignments done using the CAD Tools (Active-HDL) electronically. We will give you instructions on how to do this.
The last column indicates the pages of the textbook that are relevant to the lecture material. I am counting on you to read this twice – once before we cover it in class, and once again to make sure you understand it. The textbook is also a good source of additional explanations and examples.
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Week |
Day |
Date |
Topic |
Textbook reading |
|---|---|---|---|---|
|
#1 |
W |
9/28 |
Introduction and Course Overview |
pp. 1-9 |
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F |
9/30 |
Binary numbers, Boolean algebra |
Appendix A, pp. 33-36 |
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#2 |
M |
10/3 |
Boolean algebra and theorems, gates |
pp. 37-45 |
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W |
10/5 |
Boolean functions and logic circuits |
pp. 45-56 |
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F |
10/7 |
2-level logic, canonical forms |
pp. 57-66 |
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#3 |
M |
10/10 |
Graphical representations of Boolean functions |
pp. 66-77 |
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W |
10/12 |
Karnaugh Maps/Logic minimization |
pp. 66-77 |
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F |
10/14 |
2-level logic minimization |
pp. 95-104 |
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#4 |
M |
10/17 |
Structured logic implementation: ROMs, PLAs |
pp. 170-209 |
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W |
10/19 |
Structured logic implementation: PLAs, PALs |
pp. 170-209 |
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F |
10/21 |
Multi-level logic circuits |
pp. 77-85 |
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#5 |
M |
10/24 |
Combinational logic delay and glitches |
pp. 131-140 |
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W |
10/26 |
Ripple-carry adder; carry-lookahead adder |
pp. 239-249 |
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F |
10/28 |
ALU, multiplier design |
pp. 249-257 |
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#6 |
M |
10/31 |
Registers |
pp. 261-279 |
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W |
11/2 |
Registers and clocking: counters and shift registers |
pp. 289-294 |
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F |
11/4 |
Sequential circuits: Finite state machines and state diagrams |
pp. 310-323 Class notes |
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#7 |
M |
11/7 |
State diagrams/State tables |
pp. 324-335 Class notes |
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W |
11/9 |
Verilog for combinational and sequential circuits |
Class notes |
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F |
11/11 |
Veteran's Day (Holiday) |
Class notes |
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#8 |
M |
11/14 |
Control/Datapath design |
Class notes |
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W |
11/16 |
Simple processor design |
Class notes |
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F |
11/18 |
Implementing FSMs Mealy vs. Moore FSMs |
pp. 335-342, Class notes |
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#9 |
M |
11/21 |
Verilog HDL: combinational logic |
Class notes |
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W |
11/23 |
Verilog HDL: sequential logic |
Class notes |
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F |
11/25 |
Happy Thanksgiving! |
Class notes |
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#10 |
M |
11/28 |
Simple processor design |
Class notes |
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W |
11/30 |
Simple processor design |
Class notes |
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F |
12/2 |
Simple processor design |
Class notes |
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#11 |
M |
12/5 |
Non-gate logic: Tristate and open-collector drivers |
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W |
12/7 |
Clock skew; asynchronous inputs |
6.2 |
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M |
12/12 |
Final Exam |
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Other UW Time Schedules
Autumn 2005 final exam schedule (CSE370 final exam may differ in time)