This tutorial will introduce the concept of modules that we will use later to construct larger, more complex, components from more primitive ones. You will use the to the 1-bit full adder you designed in Tutorial #1 and show you how you can use it in as a module in another schematic. You will connect the full-adder to a test fixture module written in Verilog. The test fixture will "exercise" the full-adder circuit and verify that it operates properly. Then, you will replace the schematic module for the full-adder with a Verilog module that implements the same functions. After completing this tutorial you will know how to:
Even though this tutorial will show you all you need to know to create basic Verilog modules, you should experiment with Active-HDL on your own. You will find that there are many tools and options that have been left out of this tutorial for the sake of simplicity. By experimenting with these tools on your own, you will become more proficient with Active-HDL, and you may find different methods that better suit your style, while still achieving the same design goals.
Additionally, you should visit the Active-HDL Tips web page for help (it is linked from the Hardware Lab’s homepage under “Help/Technical Tips/Aldec Active-HDL”). This web page will be updated periodically with new hints and tips based on input from students and faculty who use the Active-HDL tools. We encourage you to review this web page and email any suggestions/tips of your own to the Hardware Lab manager or your instructor.
* If you have forgotten how to use the “More…” button refer back to Tutorial #1 for directions.
What is a test fixture? Test fixtures are used to test and/or simulate a design or a component of a design. A test fixture is usually generated in Verilog because we don't want to bother generating logic. We are interested only in its functionality, namely, to drive the input signals of a circuit we want to check and sample the outputs to verify they are correct. We are particularly interested in “self-checking” test fixtures that check the outputs and report an error automatically so that we don’t have to look at the waveforms.
For this tutorial, the test fixtures are
provided. In later assignments, you'll have to write your
own. Make sure to take some time to read through the Verilog code
of the text fixture.
Before using components as part of other components, you should test them, just like you test procedures before using them in programming. In Tutorial #1, you used a simulation and a waveform to verify your 1-bit full adder. Test fixtures will not eliminate the need to use the debugging skills you learned in the first tutorial, but they will make verifying the correctness of a design faster and simpler. This is accomplished by the test fixture’s ability to send messages to the Console in addition to producing waveforms.
At some point, when you have learned Verilog a bit better, you will be writing your own test fixtures. For this tutorial, we will provide you with a test fixture file to test your design. (It’s pretty easy to follow these examples to generate your own Verilog text fixtures.) The code provided will test a number of cases and print a series of messages to help you find errors, if any. These messages will be printed to the Console and a text file.
Active-HDL can create block symbols from your compiled schematic designs and Verilog source code files in the Symbols Toolbox. We will create block symbols for the full adder you designed earlier and the full adder test fixture. This portion of the tutorial will walk you through placing a block symbol for the full adder into a new schematic and connecting it to a test fixture to ensure that it functions properly.
The correct way to design is to write a test
every component you design. If you
change the design, all you have to do is re-run the test fixture to
you have not introduced new errors. As
a practical matter, we typically write test fixtures only when the
get reasonably complicated. Whether we
would write a test fixture for a full adder is mostly a matter of how
optimistic we are. It is best to assume
that you are going to make mistakes, and the sooner you find them, the
your life is going to be. Additionally, test fixtures come in handy
drive signals for a waveform simulation. Imagine a more complicated
several multi-bit signals. Explicitly setting stimulators for each bit
is what you would have to do using stimulators) is time consuming and
simulating a design more difficult.
Simulate your design and make sure that your
full-adder circuit checks out, that is, that the test fixture prints
messages that indicate every test passed.
Now we'll turn to creating a Verilog module.
It will implement exactly the same functionality as the full-adder
schematic, but do so using Boolean expressions rather than gates.
To verify your Verilog module follow the same procedure as above with the test fixture, by substituting the full adder schematic with your new Verilog module. First, Open the Symbols Toolbox and find the name of your design to expand your design’s part list. You should see a “Units without symbols” list. Expand it and find the name of your Verilog full adder. Select it, and notice that a block symbol appears in the bottom window of the Symbols Toolbox. Add this part to your schematic by dragging the symbol from the bottom window. Notice that this component no longer appears in the “Units without symbols” list after it has been added to the schematic once.
You should now understand how to design your own schematic and Verilog combinational logic modules. You should also have a sense for what a test fixture does and the kind of Verilog code that goes into these testing modules. Continue to experiment with Active-HDL, and begin to read and try to understand the Verilog code we provided you with for this tutorial.
Remember to check with the Active-HDL Tips webpage for helpful information on known bugs and shortcuts. Additionally, we would appreciate your suggestions for improvements/additions to the tutorials and the Active-HDL Tips webpage. Email your comments to your instructor or the Hardware Lab manager.
*Remember to visit the UW CSE Active-HDL Tips web page for hints and tips.