CSE370 Tutorial 2 - Introduction to Verilog in Aldec Active-HDL 6.1
Schematic Modules, Verilog Modules, and Test Fixtures
Objectives
This tutorial will introduce the concept of modules that we
will use later to construct larger, more complex, components from more
primitive ones. You will use the to the 1-bit full adder you
designed in
Tutorial #1 and show you how you can use it in as a module in another
schematic. You will connect the full-adder to a test fixture
module written in Verilog. The test fixture will "exercise" the
full-adder circuit and verify that it operates properly. Then,
you will replace the schematic module for the full-adder with a Verilog
module that implements the same functions. After completing this
tutorial you will know how to:
- Design using modules;
- Test components using test fixtures;
- Use block symbols in Active-HDL; and
- Create a Verilog module and test it as
well.
Even though this tutorial will show you all you
need to know
to create basic Verilog modules, you should experiment
with
Active-HDL on your own. You will find that there are many tools and
options
that have been left out of this tutorial for the sake of simplicity. By
experimenting with these tools on your own, you will become more
proficient
with Active-HDL, and you may find different methods that better suit
your
style, while still achieving the same design goals.
Additionally, you should visit the Active-HDL
Tips web page for help (it is linked from the Hardware
Lab’s homepage under “Help/Technical Tips/Aldec Active-HDL”). This
web page
will be updated periodically with new hints and tips based on input
from
students and faculty who use the Active-HDL tools. We encourage you to
review
this web page and email any suggestions/tips of your own to the Hardware Lab manager or
your instructor.
Start Active-HDL
- Open
Active-HDL.
- Select the “Open existing workspace” option and select your
workspace from Tutorial #1 in the window, or click the “More…” button
to attach and open it (Figure 1).
Figure
1
- Click
OK.
* If you have forgotten how to use the
“More…” button
refer back to Tutorial #1 for directions.
Test Fixtures
What is a test fixture? Test fixtures are used to
test
and/or simulate a design or a component of a design. A test fixture is
usually
generated in Verilog because we don't want to bother generating logic.
We are interested only in its functionality, namely, to drive the input
signals of a circuit we want to check and sample the
outputs to verify they are correct. We are particularly interested in
“self-checking” test fixtures that
check the outputs and report an error automatically so that we don’t
have to
look at the waveforms.
Note:
For this tutorial, the test fixtures are
provided. In later assignments, you'll have to write your
own. Make sure to take some time to read through the Verilog code
of the text fixture.
Before using components as part of other components, you
should test them, just like you test procedures before using them in
programming. In Tutorial #1, you used a simulation and a waveform to
verify
your 1-bit full adder. Test fixtures will not eliminate the need to use
the
debugging skills you learned in the first tutorial, but they will make
verifying
the correctness of a design faster and simpler. This is accomplished by
the
test fixture’s ability to send messages to the Console in addition to
producing
waveforms.
At
some point, when you have learned Verilog a bit better, you will be
writing your own test fixtures. For
this tutorial, we will provide you with a test fixture file to test
your design. (It’s pretty easy to follow these examples to generate
your own Verilog text fixtures.) The
code provided will test a number of cases and print a series
of messages to help you find errors, if any. These messages will be
printed to
the Console and a text file.
- You
will need to add the following a file to your design: FA_tf.v (this test
fixture tests a 1-bit full adder). Download this file and place
it in a folder you'll remember (e.g., a personal folder).
- Double-click “Add
New File” in the Design Browser.Now,
click the “Add Existing File” button.
- Navigate to the class folder, which contains these files, click
the “Make local copy” box, and add the test fixture for the full adder
(see Figure 2 on the following page). Notice it
is added to the design hierarchy in the Design Browser. We use the
naming convention: <design name>_tf.v to name test fixtures so
that it is easy to associate test fixtures with the components they
test. If you choose different names for your full adder, make sure you
rename these test fixtures by right-clicking the file in the Design
Browser.
Figure
2
- Double-click
the test fixture in the Design Browser to open this file in the main
window.
- You
do not need to understand the code completely, but read through the
code and
try to understand what it is doing and why it is doing it. Figure 3 (on the following
page) shows the code for the full adder test fixture with areas of
interest
circled in red. If you renamed the file, change the title and the
module name
to reflect this change. (Optional) This test fixture prints its
results
to a file as well as the Console by using the “$fopen()” statement. You
may
change the name of the text file that the test fixture prints to by
changing
the name in the parameter of the fopen statement (see Figure
3). Once you have familiarized yourself with
the code, save it and then compile it. If you choose to modify
this
file, save the file after each modification, and recompile it after you
have
saved it.
Figure 3
Block Symbols
Active-HDL can
create block
symbols from your compiled schematic designs and Verilog source code
files in
the Symbols Toolbox. We will create block symbols for the full adder
you
designed earlier and the full adder test fixture. This portion of the
tutorial
will walk you through placing a block symbol for the full adder into a
new
schematic and connecting it to a test fixture to ensure that it
functions
properly.
- Add
a new empty block diagram file called: <design name>_test. Do
this by
double-clicking “Add New File” in the Design Browser, select the “Block
Diagram” option under the Empty Files tab, and enter the name in the
“Name”
field. Then, click OK. Remember to reset
the design’s target HDL.
- Open
the Symbols Toolbox. Find the name of your design, and expand your
design’s
part list. You should see a “Units without symbols” list. Expand it and
find
the name of your full adder schematic. Select it, and notice that a
block
symbol appears in the bottom window of the Symbols Toolbox. Add this
part to
your schematic and notice that this component no longer appears in the
“Units
without symbols” list.
- Repeat
step 2 to add the symbol for full adder test fixture to the schematic.
- You
can edit block symbols by right clicking the part in the schematic and
selecting the “Edit” option. (Note: if this option is not
available,
save, close, and reopen the file and try again.) While in edit mode,
you can
drag the pins to a new position within the symbol. Clicking outside of
the part
will end the edit session, and you will be prompted to save your
changes.
- The test fixture will drive the input signals of the full
adder and test the full adder’s outputs. Connect the two units using
wires. The
outputs of the test fixture connect to the corresponding inputs of the
full
adder, and the inputs of the test fixture connect to the corresponding
outputs
of the full adder (Figure 4).
Figure
4
- Now
that the units are connected, save, run the check diagram tool, and
compile the
test schematic.
- Set
the test schematic as the top level, close any waveforms, initialize a
simulation, and run the simulation for 80 ns. If you have forgotten how
to do
any of these steps, refer to Tutorial #1.
- The
Console, along with a text file, will contain the results
of the simulation. If all eight cases passed, end the simulation, and
continue
with the tutorial. If not, there may be some problems with your full
adder (see
Tutorial #1 for examples on how to debug your design).
The correct way to design is to write a test
fixture for
every component you design. If you
change the design, all you have to do is re-run the test fixture to
make sure
you have not introduced new errors. As
a practical matter, we typically write test fixtures only when the
components
get reasonably complicated. Whether we
would write a test fixture for a full adder is mostly a matter of how
optimistic we are. It is best to assume
that you are going to make mistakes, and the sooner you find them, the
easier
your life is going to be. Additionally, test fixtures come in handy
just to
drive signals for a waveform simulation. Imagine a more complicated
design with
several multi-bit signals. Explicitly setting stimulators for each bit
(which
is what you would have to do using stimulators) is time consuming and
can make
simulating a design more difficult.
Simulate your design and make sure that your
full-adder circuit checks out, that is, that the test fixture prints
messages that indicate every test passed.
Creating a Verilog Module
Now we'll turn to creating a Verilog module.
It will implement exactly the same functionality as the full-adder
schematic, but do so using Boolean expressions rather than gates.
- Add a new Verilog file to the design.
To do this double-click on the “Add New File” in the Design Browser,
then select the “Wizards” tab, and click on the “Verilog Source Code
Wizard”. Then, click OK.
Figure 5
- In the New Source File Wizard, make
sure that the box is checked next to the “Add the generated file to the
design” option. Click the Next button. Note: this window is not
shown.
- In the “Type the name of the source
file to create” field, enter the name of your verilog file using a
descriptive name. You must try to keep them distinct so as
not to confuse both you and the tool. Do not use the same name
that you named your design or workspace. Also, do not fill in the
name of the module; leave this field blank. Active-HDL will use the
source files name for the module by default. This just makes it easier
for everyone to keeps things straight. Click the Next button
(Figure 6).
Figure 6
- The next window that opens is where
you add your input and output ports. These are the inputs and outputs
of your module. To add ports, click the “New” button (see Figure
7). Choose whether you want an input or output port by clicking the
desired radio button located under the “Port Direction” heading.
In the “Name” field, type the name of the port. We will only be using
1-bit ports, so ignore the “Array Indexes” fields for now. Your screen
should look like Figure 7. If so, then click the Finish button.
Figure 7
- Aldec will open a Verilog file with
the module, inputs, outputs, and wires already declared (see Figure 8).
Locate the section of the file that contains the comment: ” // -- Enter
your statements here -- //”. In this area
you will insert the code to give CO and S its value. The code should
contain an assign statement along with the AND operator ( “&” ), OR
operator (“|”), and the NOT operator (“~”). Below is an example line of
code where X, Y, Z are inputs and W is an output: "assign W = ( Y & Z
) | ( X & ~ Z);"
Figure
8
- Save
and compile your
verilog module. As in tutorial #1, a green checkmark should appear in
Design
Browser next to your Verilog module if it successfully compiles and a
red “x”
will appear if problems occur.
-
To verify your Verilog module follow the same procedure as above
with the test fixture, by substituting the full adder schematic with
your new Verilog module. First, Open the Symbols Toolbox and find the
name of your design to expand your design’s part list. You should see a
“Units without symbols” list. Expand it and find the name of your
Verilog full adder. Select it, and notice that a block symbol appears
in the bottom window of the Symbols Toolbox. Add this part to your
schematic by dragging the symbol from the bottom window. Notice that
this component no longer appears in the “Units without symbols” list
after it has been added to the schematic once.
Concluding Remarks
*Remember to visit the UW
CSE Active-HDL Tips web page
for hints and tips.
Comments to: cse370-webmaster@cs.washington.edu (Last Update:
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