//--------------------------------------------------------------------------------------------------
//
// Title       : SerialEncoder
// Design      : PALs
// Author      : cse
// Company     : uw
//
//-------------------------------------------------------------------------------------------------
//
// File        : SerialEncoder.v
// Generated   : Tue Feb 17 19:57:33 2004
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {SerialEncoder}}
module SerialEncoder ( CLK, TXD ,byteReady ,done ,char, reset);
	
	input byteReady ;
	wire byteReady ;
	input [7:0] char ;
	wire [7:0] char ;
	input reset;
	wire reset;
	input CLK;
	wire CLK;
	
	output TXD ;
	reg TXD ;
	output done ;
	reg done ;

	always @(posedge CLK) 
		begin
			
		end
	
endmodule