Implement and simulate the last question of homework 6 as a
6.23 (Shift Register Design )
Design the basic cell of a universal shift register to the following
specifications. The internal storage elements will be positive
edge-triggered D flip-flops. Besides the clock, the shifter stage has
two external control inputs, S0 and S1, and three external data inputs,
SR, SL, and DI. SR is input data being shifted into the cell from the
right, SL is data being shifted from the left, and DI is parallel load
data. The current value of the flip-flop will be replaced according to
the following settings of the control signals:
S0 = S1 = 0: replace D with DI; S0 = 0, S1 = 1: replace D with SL; S0 =
1, S1 = 0: replace D with SR; S0 = S1 = 1: hold the current state.
Now build a 4-bit shift register using your verilog module, with SL
shifting from LSB toward MSB, and SR shifting from MSB toward LSB.
Simulate your work to check for correct operation, and compile it into
your PAL. Wire
up your shift register with LEDs and switches, similar to your
implementation in lab 5. Demonstrate correct operation and your verilog
module to the TA.