CSE370 Laboratory Assignment 6

Counters and Finite State Machines

Distributed: 18 February 2004
Due: 25 February 2004

Objectives

Tasks

1. We'll start by building a 4-bit, loadable and resettable binary counter with count enable.  In fact, it will be a component very similar to the '163 counter we've seen so often and whose pins and internal logic diagram are reproduced below.  We've prepared a skeleton Verilog file for the counter that you must complete.  Note that it uses uncomplemented inputs (active high) for the load and reset signals.  You will also need a pin assignment file to direct the tools to assign signals to specific pins of your PAL (you do not need to change this file, but if you do, keep the same structure).
    
   
   Pin diagram for '163 counter with synchronous reset
   
    
   To set the tool to use the pin assignment file (.CTL extension), in the Synthesis Options window (step 7 & 8 of Tutorial 3) on the General tab click the check box "Use Custom CTL file." Next Click on the Browse button and point the program at your CTL file. Click OK.
    
   
   After you've compiled your circuit, look at the synthesis report and study the equations for the flip-flop inputs.  Are they what you expected?  Convince yourself that they match the logic diagram below for the '163 (that they are logically equivalent).  Do they differ in any substantial way?
   
   
   Internal logic diagram for the '163 (the G2 input of the flip-flops is an enable signal, the 3R input is the synchronous reset signal, and the M1 input is the load signal).
   
   Connect your counter to 4 input switches and 4 output LEDs.  Run your counter using the push-button and verify that it is counting properly. Make sure to use the enable, load, and clear inputs at various times and check that all work as expected. Show your work to the TA to be checked off.
    
   

2. We will be constructing a simple game based on an FSM that we will build using our 22v10 PAL.  The game uses 7 LEDs and two push button switches. It functions as a simple tug-of-war variant.  The game starts with the middle LED turned on.  When one button is pressed, the light shifts one to the left, when the other button is pressed, the light shifts one to the right.  The objective is to push the button on one side fast enough to turn on the LED on an end of the line.  When one of these LEDs turns on, one player is the winner and the game must be reset.
   
   Below is a state diagram for the game FSM.  In addition to the main functionality of this state diagram, we also need to ensure that the push buttons only generate a single width pulse for this FSM.  To be extra sure, we'll use a flip-flop to create a single pulse whenever the push button input changes from 0 to 1.  This is similar to one of the exercises in the last written assignment.
   
   
   State diagram for the game FSM.
   
   We are providing you with a Verilog file that implements the sequential logic for this game and the pin assignment file to go with it.  Compile this into your PAL. When putting the PAL on your breadboard, use two slider switches for the left and right inputs and use the push button to generate a clock signal.  Verify that the game works as advertised.  Remember to reset the FSM to start each game.
   
   Two more push buttons have been programmed to work exactly the same as your clock push button - a single pulse generated whenever the button is pressed.  BTN2 and BTN3 have been set up to generate their pulses on the signals labelled O2 and O3 on the J1 breadboarding connector (see the map in lab assignment #5).  Connect the left and right inputs to the O2 and O3 push buttons (instead of the slider switches) and change the clock to free running mode.  Play the game for real!  Remember to reset the FSM to start each game.
   
   Look carefully through the report generated from compiling to the PAL.  Are the logic equations what you'd expect? 
   
   
3. If you checked out your game carefully when using the push buttons for inputs, you may have noticed that game is not fair to both players?  What happens if both the left and right inputs are true in the same clock cycle?  The correct behavior should be that the LED doesn't move in either direction.  What does the FSM provided do?  Make any modifications necessary to make the game fair.  Demonstrate your fair version of the game to the TA to complete this assignment.
   
   
4. Implement and simulate  the last question of homework 6 as a verilog module:
   
   
   6.23 (Shift Register Design ) Design the basic cell of a universal shift register to the following specifications. The internal storage elements will be positive edge-triggered D flip-flops. Besides the clock, the shifter stage has two external control inputs, S0 and S1, and three external data inputs, SR, SL, and DI. SR is input data being shifted into the cell from the right, SL is data being shifted from the left, and DI is parallel load data. The current value of the flip-flop will be replaced according to the following settings of the control signals:
   S0 = S1 = 0: replace D with DI; S0 = 0, S1 = 1: replace D with SL; S0 = 1, S1 = 0: replace D with SR; S0 = S1 = 1: hold the current state.
   
   
   Now build a 4-bit shift register using your verilog module, with SL shifting from LSB toward MSB, and SR shifting from MSB toward LSB. Simulate your work to check for correct operation, and compile it into your PAL. Wire up your shift register with LEDs and switches, similar to your implementation in lab 5. Demonstrate correct operation and your verilog module to the TA.