Please show all of your work.Your solutions must be
legible…we will not spend time trying to decipher poorly written
assignments.
Produce a completed ant-brain design (AntBrain Lecture),
in Active-HDL, with documentation, including the following additions.
1) Crumbs in cell
Ant eats
crumbs in every cell it visits. The maze map is the crumb map. It's
128x128x8 bits, as shown in the lecture slides. The MSB is '0' in all
cells, and you should write the 8 bits you read (eating crumbs) back to
the memory location with the MSB set to '1' (leaving a crumb).
2) You need to design a memory controller in the form of a state machine to talk to the SRAM.
3) You
need to deal with startup, exit states, and at least one module must be
written in Verilog.
Hand in:
Schematics, with
top-level block diagram
any Verilog you write
documentation of SRAM memory controller state-machine design
Label all pages with your name and section
number, please....
EXTRA CREDIT:
(Indicate if you want this to count as 1 homework or as 1 quiz, or one
of each if you do both options). Hand
in as a separate document marked "Ant Maze Extra Credit".
Option 1: Invent a way to capture the crumb
map from
Active simulation runs, and plot the maze map on the PC (yes, you'll
probably have to write some code).
Turn in print outs of at least two different maze runs. You may turn
this in in the form of an executable program, if you wish.
Let's see that ant go!
Option 2: Design an ant that can handle a
maze with islands. Prove that it works by starting it on an island from
which your original ant can't escape. Hand in print-outs to show your
work, documenting your changes to the design and explaining why your
ant works. If you've also done Option 1, use the same technique to plot
your result.