CSE370 Assignment 6

Distributed: 12 February 2004
Due: 23 February 2004

Reading:

1. Katz/Borriello, Contemporary Logic Design, Chapter 6
   

Exercises:

1. CLD-II, Chapter 6, problem 6.4.
   
2. CLD-II, Chapter 6, problem 6.5.
3. CLD-II, Chapter 6, problem 6.11.
4. CLD-II, Chapter 6, problem 6.15.
5. CLD-II, Chapter 6, problem 6.17.
6. CLD-II, Chapter 6, problem 6.23. Use Active-HDL to draw your schematic; simulate its correct operation. Turn in completed schematic and waveform.
   

Rationale:

• To begin understanding the basic building blocks of sequential circuits.
• To learn the use of simulation tools and hardware description languages for sequential circuit blocks.