CSE370 Assignment 5
Distributed: 2 February 2004 ---revised 2/6/04
Due: 11 February 2004
- Katz/Borriello, Contemporary Logic Design, Chapter 5
- CLD-II, Chapter 4, problem 4.23.
- CLD-II, Chapter 4, problem 4.25.
- CLD-II, Chapter 4, problem 4.26.
- Construct a 5-bit ripple-carry adder with five full-adder blocks
Aldec ActiveHDL. First construct - out of basic gates from the lib370
library - a single-bit full-adder block to reuse. Verify your design
using simulation, turn in the schematic and timing waveforms
showing what happens when you have
"11110" and "00001" as the numbers to be added and you change the
to "00010". How long does it take the sum to get to the right value?
this experiment starting with "11010" and "00010" and changing the
to "00101". Explain the differences between the two cases.
- Repeat the previous problem but now construct a 5-bit
Use the same full-adder module as the previous problem. Repeat the two
How much faster is the carry-lookahead adder in both cases? Explain the
with the result of the previous problem. How do your circuits
from this problem
and the previous one compare in the total number of gates they use
consider gates in all sub-blocks)?
- Design a 10-bit carry-select adder for unsigned numbers. It
hierarchically at the schematic diagram level and include 3 instances
the 5-bit ripple-carry adder module you created in the previous
also need to include some multiplexers. Make sure that your 10-bit
adder also has a carry-out in case anyone would ever want to use it to
build a larger adder. Verify its operation for "1111111111" +
Turn in the schematic and simulation waveform.
- To design hierarchical combinational circuits from high-level
- To better appreciate the differences between ripple-carry,
carry-lookahead, and carry-select adders.
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