//--------------------------------------------------------------------------------------------------
//
// Title       : lfsr8
// Design      : lab6
//
// Description : This is an 8-bit LFSR that generates a maximal length sequence
//
//-------------------------------------------------------------------------------------------
`timescale 1ns / 1ns

module lfsr8 (clk, reset, rand);
   input clk, reset;
   output [7:0] rand;
   reg [7:0] rand;			 // Required for always block assignment
   wire [7:0] nxt_rand;
   
   // These assigns implement the combinational logic for the 
   // register inputs
   assign     nxt_rand[0] = rand[7] ^ rand[6] ^ rand[5] ^ rand[0];
   assign     nxt_rand[7:1] = rand[6:0];
   
   // This always block implements the "rand" register
   always @(posedge clk) begin
      if (reset) begin
	 rand <= 1;
      end else begin
	 rand <= nxt_rand;
      end
   end

endmodule