//------------------------------------------------------------------------ // Title : game.v // Descrition : This module implements the FSM for the reaction game. // It only has one player and must be extended to two. //--------------------------------------------------------------------------- `timescale 1ns / 1ns module game (clk, reset, startButton, loadCnt, tc, startLight, stopA, winA, stopB, winB); input clk, reset; input startButton; // Button to start the game output loadCnt; // Load the counter output startLight; // Turn on the start light input tc; // Terminal count from counter input stopA, stopB; // Player stop buttons output winA, winB; // Player Win lights // Reg declarations for always block assignments reg loadCnt; reg startLight; reg winA, winB; // State encoding parameter IDLE=0, // Reset state START=1, // Start the game WAIT=2, // Wait for stop button AWIN=3; // Player A wins! // The state register reg [1:0] state, nxt_state; // This block implements a simple state register always @(posedge clk) begin if (reset) state <= IDLE; else state <= nxt_state; end // This block implements the next state function // and the output function always @(state or startButton or tc) begin // Defaults loadCnt = 0; startLight = 0; winA = 0; winB = 0; case (state) // Reset state IDLE: begin if (startButton) begin loadCnt = 1; nxt_state = START; end else begin nxt_state = IDLE; end end // Counter has been loaded; wait for it to finish START: begin if (tc) nxt_state = WAIT; else nxt_state = START; end // Counter has finished, turn on the start light and // wait for stop button WAIT: begin startLight = 1; if (stopA) nxt_state = AWIN; else nxt_state = WAIT; end // Stop button has been pushed; turn on win light AWIN: begin winA = 1; if (startButton) begin nxt_state = START; loadCnt = 1; end else begin nxt_state = AWIN; end end endcase // case(state) end // always @ (*) endmodule // count8