CS 370 - Spring 2004
Introduction to Digital Design
Instructor: Carl Ebeling

Homework Set 9
DUE: Friday, June 4 , 2004, Start of class

Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.

The weekly assignments are due at the beginning of class. Assignments handed in during or immediately after class will incur a 10% penalty. We will penalize your assignment 10% per day for each additional day late. Please show all of your work. Your solutions must be legible…we will not spend time trying to decipher poorly written assignments.

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1. (100 points) Design a circuit that keeps track of the number of people in a room. The room has one door, with two photocell detectors, Dout and Din, one just outside (Dout) and one just inside (Din) the door. If nothing breaks the light beam, the detector outputs a 1; otherwise, it outputs a 0. When a person enters (exits) the room, he or she first breaks the beam outside (inside) the door, and then breaks the beam inside (outside) the door. The detectors are spaced close enough together that the person will block both beams while in the door. Assume that only one person enters exits at a time and that the room holds a maximum of 15 people.

Design a circuit that gives a count of the number of people in the room. Your circuit should detect error sequences and turn on an Error light. Note, however, that it is OK for someone to change their mind halfway through the door and turn around.

First draw a block diagram of the design as a datapath and a state machine controller showing the control signals that need to be generated. Next draw a state diagram for the controller. Include an error state which you go to, and stay in, if you detect an error. Finally, write the Verilog for your design. You should write this as two modules, one for the controller and one for the datapath You do not have to use Active-HDL and you do not have to simulate it. We care about the overall design, not the syntax. (Hint: 8 states should suffice if you use a Mealy machine.)

2. (100 points)  Design the x370 Model 2.  This involves adding the data memory to your processor and implementing the load and store instructions. You will find the dram module in the lib370 library.

You may find it convenient to use assignment statements in your schematics to reduce the number of random logic gates you have to draw. Look for the menu item called Continuous Assignment. This will create a block in which you can write assign statement. Note: If the name you are assigning to does not appear in the schematic, i.e. it is a temporary variable, then you write:

wire foo = A & B;

Instead of:

assign foo = A & B;

We will give you a program to test your resulting processor design. You should turn in a copy of your schematics and Verilog programs, plus a screen shot showing the contents of your register file and data memory at the end of simulation. You must also submit a copy of your project electronically – details will be posted later.