CS 370
- Spring 2004
Introduction to Digital
Design
Instructor:
Homework Set 6
DUE:
Collaboration Policy:
Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.
Late Homework Policy:
The weekly assignments are due at the beginning of class. Assignments handed in during or immediately after class will incur a 10% penalty. We will penalize your assignment 10% per day for each additional day late.
Please show all of your work. Your solutions must be legible…we will not spend time trying to decipher poorly written assignments.
1. (40 points) Design and test, using Active-HDL, a 16-bit ALU that executes the functions described in the following table. The OP Code has three bits and tells the ALU which operation to perform on the two inputs, A and B. Note that only five of the possible eight OP codes are used – you might think about how to implement other interesting functions.
|
Operation |
ALU result |
OP Code |
|
ADD |
A + B |
0 |
|
SUB |
B –
A |
6 |
|
INC |
A + 1 |
2 |
|
Pass A |
A |
3 |
|
XOR |
A XOR B |
1 |
Design your ALU using a bit-slice approach. That is, design a single bit
of the ALU that can be copied N times to create an N-bit ALU. You should
with the implementation of your carry-lookahead adder using the components from
HW5. You should be
able to just replace the 1-bit adder with the ALU slice you design here, adding
the ALU control signals. You do not have to modify the carry-lookahead
units at all. Look at the notes for the ALU
bit-slice we went over in class. Figure out how to implement the
functions given here using that ALU. Although I have chosen the OP Code
to make things somewhat easy, you will have to convert this 3-bit OP Code into
the control signals that the ALU needs.
Test your 16-bit ALU
using the test fixture provided in the class homework folder. Hand in printouts of the
schematics/Verilog files of your design, along with a printout of the console
that shows that your ALU works correctly.
2. (60 points) Implement the following circuit that implements the controller for a laser range-finder. The range-finder works as follows: When the start button is pressed, a counter is reset and a laser pulse (ping) is emitted. The counter is then enabled until an echo is detected, at which time the counter is stopped. The value of the counter represents the distance.
Your control circuit has the following inputs:
clk,
reset
start -
Asserted when the start button is pressed.
echo -
Asserted when an echo is detected
and the following outputs:
clearCount -
Assert to clear the counter
enableCount - Assert to enable the
counter
ping -
Cause a laser pulse to be emitted.
Assert for one clock cycle.
a) Draw the state diagram for this controller.
b) Convert the state diagram to a state table.
c) Decide on a state assignment.
d) Synthesize the next state and output logic functions.
e) Draw the final circuit using Active-HDL.
f) Simulate the circuit, using the ClockGen component from lib370 to generate the clock and reset, and Stimulators for the start and echo inputs. We will give you the counter circuit as a Verilog file similar to the one in Lab #6.
Turn in everything, including your schematic and printout of the timing diagram that demonstrates that your design works.