CS 370
- Spring 2004
Introduction to Digital
Design
Instructor:
Homework Set 5
DUE:
Collaboration Policy:
Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.
Late Homework Policy:
The weekly assignments are due at the beginning of class. Assignments handed in during or immediately after class will incur a 10% penalty. We will penalize your assignment 10% per day for each additional day late.
Please show all of your work. Your solutions must be legible…we will not spend time trying to decipher poorly written assignments.
1. (25 points) Using the attached 22V10 sheet, program the increment function for a 4-bit number. This circuit has a 4-bit input D[3:0] and a 4-bit output Q[3:0], where Q = D + 1. Note that only part of the 22V10 is given here. Use pins 2,3,4,5 for the D[3:0] input and pins 22,21,20,19 for the Q[3:0] output, in that order.
2. (50 points) In this assignment, you will implement and test a complete 16-bit carry-lookahead adder using Active-HDL. You will find test fixtures for each of the components and the final circuit in the HW5 folder. Make sure you use only components from the lib370 library.
a) Design and test a 1-bit adder which has three inputs, A, B, Cin, and three outputs, Sum, P, and G, where P and G are the propagate and generate functions. You may use either a schematic with gates, or a Verilog file like you wrote for Lab#4.
b) Using your 1-bit adder, design and test a 4-bit adder component which has three input busses, A[3:0], B[3:0], Cin[3:0] and three output busses, Sum[3:0], P[3:0] and G[3:0]. (This 4-bit adder is just four independent copies of the 1-bit adder.)
c) Design and test a 4-bit carry-lookahead component that has three inputs, P[3:0], G[3:0], Cin, and three outputs, Cout[3:0], BlockP, and BlockG. BlockP and BlockG are the block propagate and block generate functions. You may use either a schematic with gates, or a Verilog file.
d) Using your 4-bit adder component and 4-bit carry-lookahead component, design and test a 16-bit carry-lookahead adder.
e) What is the size (# of gates) and delay of your 16-bit carry-lookahead adder?
f) If you continued and made a 64-bit carry-lookahead adder using these components, what would be the size and delay of that circuit?
3. (25 points) Complete the timing diagram below for the following circuit. Assume that gates and inverters have a delay of 1ns, and that the propagation delay of the register is 1ns. The vertical lines mark 1ns time; thus, the clock cycle is 10ns.
