CS 370
– Spring 2004
Introduction to Digital
Design
Instructor:
Homework Set 3
DUE:
Collaboration Policy:
Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.
Late Homework Policy:
The weekly assignments are due at the beginning of class. Assignments handed in during or immediately after class will incur a 10% penalty. We will penalize your assignment 10% per day for each additional day late.
Please show all of your work.Your solutions must be legible…we will not spend time trying to decipher poorly written assignments.
This homework assignment will be concerned mostly with using Active-HDL, although you will be practicing concepts you have used from class.
The Intro to Active-HDL Tutorial #2
continues from Tutorial #1 and covers hierarchy, signal busses and test
fixtures. The Tutorial is closely related to problem 2 of this homework. It would be a good idea to read over
problem 2 before you do the tutorial.
Work through this tutorial, making sure you understand everything that it
covers. Again, if you run into problems, send us email or try to find us.
If you have comments on how to make the Tutorial better, please send me
email.
1. (30 points) This problem involves the following function of three inputs, A, B and S: If S=0, then the output=A; if S=1, then the output=B. (This is sometimes known as an if-then-else gate.)
a) Find both the minimal SOP and POS circuit implementation of this function.
b) Using Active-HDL, enter the schematics for both these circuits in the same block diagram. Use the test fixture in the following file to test your circuits: \\ntdfs\cs\cse\courses\cse370\04sp\hw3\if_then_else_tf.v Print the waveform from your simulation. Are there glitches in the output of your circuits? Explain what causes them, and explain why the circuits have different behaviors.
c) In a new block diagram, design a single circuit implementation that does not have glitches on the output. Use the same test fixture, and print the waveform from your simulation.
2. (50 points) Design a full-adder component with inputs A, B and Cin, and outputs S and Cout.
a) Find the minimal 2-level circuit implementation for S and Cout. Make a component for this comparator using Active-HDL. Use the text fixture ...\cse370\04sp\hw3\fulladder_tf.v to test your component. Print your schematic and console output from the simulation.
b) Now design a 4-bit ripple-carry adder using four of your full-adders. Use the test fixture ...\cse370\04sp\hw3\adder4_tf.v to test your component. Print your schematic and console output from the simulation.
c) Now design an 8-bit ripple-carry adder using two of your 4-bit full-adders. Use the test fixture ...\cse370\04sp\hw3\adder8_tf.v to test your component. Print your schematic and console output from the simulation.
d) What is the worst-case delay of your 8-bit adder? (Don't look at the simulator waveforms! Why not?) What would be the size and delay of a 512-bit ripple-carry adder?
e) Now design an 8-bit carry-select adder. A carry-select adder does not wait for the low-order 4 bits to finish before starting on the high-order 4 bits. Instead, it adds the high-order 4 bits with two 4-bit adders: one uses 0 for the carry in while the other uses 1. When the carry out from the low-order 4 bits is available, it selects the appropriate high-order results and throws away the other. Use the test fixture ...\cse370\04sp\hw3\adder8_CS_tf.v to test your component. Print your schematic and console output from the simulation.
f) What is the worse-case delay of this 8-bit carry-select adder? Can you suggest how to make larger carry-select adders to achieve the smallest delay?
3. (20 points) Apply the 2-level simplification algorithm to the following functions to achieve the minimum SOP form. Show all your work: 1) List all the prime implicants, 2) list the essential prime implicants, and 3) give the final cover. You may do this graphically using a K-map, but make sure it it legible. (We are not going to be using the Quine-McCluskey method - stick to K-maps.)
a) SUM m(0,1,3,5,8,14,15)
b) SUM m(3,5,6,7,8,10,13) + d(1,4,9,15)
4. [Extra credit - 20 points] (This is a challenge for those who have extra time - you do not have to do any extra credit problems to earn a 4.0 in this class.) Design a circuit that has 9 inputs and outputs a 1 if more than 4 inputs are asserted.
a) How large is the canonical SOP circuit implementation of this function?
b) (Well, we won't try that!) Estimate the size of the minimal 2-level circuit for this function.
c) Let's use a multiple level circuit for this
function, and in fact, let's use a circuit that we've already designed that
does this counting for 3 inputs. What is the smallest and fastest circuit
you can come up with?
(Use just full-adders with a few ANDs and/or ORs. Hint: You can do it
with less than 8 full-adders.)
(Don't make an Active-HDL design for this.)