CSE 370 Autumn 2004

Course Calendar 

This is the schedule of lectures and related readings, homework due dates, and quiz and exam dates.

You can expect a homework assignment every week. Assignments will typically be handed out on Wednesday in class, and due the following Friday at the beginning of class. We may ask you to submit assignments done using the CAD Tools (Active-HDL) electronically. We will give you instructions on how to do this.

The last column indicates the pages of the textbook that are relevant to the lecture material. I am counting on you to read this twice – once before we cover it in class, and once again to make sure you understand it. The textbook is also a good source of additional explanations and examples.

Week	Day	Date	Topic	Textbook reading
#1	M	3/29	Introduction and Course Overview	pp. 1-9
	W	3/31	Binary numbers, Boolean algebra Assignment #1 distributed	Appendix A pp. 33-36
	F	4/2	Boolean algebra and theorems, gates	pp. 37-46
#2	M	4/5	Boolean functions and logic circuits Example circuits: decoders & multiplexors	pp. 47-56
	W	4/7	2-level logic, canonical forms Assignment #2 distributed	pp. 57-66
	F	4/9	Graphical representations of Boolean functions Assignment #1 due; Quiz 1	pp. 66-77
#3	M	4/12	Karnaugh Maps/Logic minimization	pp. 66-77
	W	4/14	2-level logic minimization no big K-maps or Quine-McCluskey Assignment #3 distributed	pp. 95-104
	F	4/16	Structured logic implementation: ROMs, PLAs Assignment #2 due	pp. 170-209
#4	M	4/19	Structured logic implementation: PLAs, PALs	170-209
	W	4/21	Multi-level logic circuits Assignment #4 distributed	pp. 77-85
	F	4/23	Combinational logic delay and glitches Assignment #3 due;  Quiz 2	pp. 131-140
#5	M	4/26	Ripple-carry adder; carry-lookahead adder	pp. 239-249
	W	4/28	ALU, multiplier design Assignment #5 distributed	pp. 249-257
	F	4/30	Feedback: latches and registers Assignment #4 due	pp. 261-279
#6	M	5/3	Registers and clocking: counters and shift registers	pp. 289-294
	W	5/5	Register-transfer design: datapath/control structure Assignment #6 distributed	Class notes
	F	5/7	Datapath/control examples Assignment #5 due;  Quiz 3	Class notes
#7	M	5/10	Finite state machines: simple sequencers/counters	pp. 310-323
	W	5/12	State machines, state diagrams Assignment #7 distributed	pp. 324-335
	F	5/14	Mealy vs. Moore FSMs Assignment #6 due	pp. 335-342, Class notes
#8	M	5/17	Implementing FSMs	pp. 335-342, Class notes
	W	5/19	Verilog HDL: combinational logic Assignment #8 distributed	Class notes
	F	5/21	Verilog HDL: sequential logic Assignment #7 due;  Quiz 4	Class notes
#9	M	5/24	Simple processor design	Class notes
	W	5/26	Simple processor design	Class notes
	F	5/28	Simple processor design	Class notes
#10	M	5/31	Holiday
	W	6/2	Non-gate logic: Tristate and open-collector drivers
	F	6/4	Clock skew; asynchronous inputs Assignment #8 due Quiz 5	6.2
#11	M 2:30	6/7	Final Exam

Other UW Time Schedules

UW Academic Calendar

Autumn 2004 final exam schedule (CSE370 final exam may differ in time)