CSE370 Laboratory Assignment 8

Serial Line Input to an LCD

Distributed: Nov. 30, 2004
Due: In one week-- Beginning of Lab time Dec. 7-8

Objectives

In this lab, you will complete the class project which is to connect an LCD display to a serial line from a PC.  As you press keys on the PC keyboard – with the aid of HyperTerminal, a serial communications program – the corresponding characters will be displayed upon your LCD.

 

You should work with your partner on this assignment. You should fully design and simulate this circuit before you try to construct it. You should do as much as you can before attending lab session. As with the previous assignment, you will have an extra week to complete the lab.

Overview

Your goal is to design a circuit which can receive characters via the RS232 serial line protocol and subsequently write them to your LCD display.  You will use the same three PALs from the previous lab, but you will extend only two of them: the main controller PAL and the PAL which was previously just an 8-bit tri-state driver.  The command decoder from the previous lab should not need to be modified.

HyperTerminal

The screen shot below shows how to configure HyperTerminal.

Note: You may experience a peculiar problem with HyperTerminal that the MSB of the character changes when you repeatedly press the same key on the keyboard. If this happens to you, here is the fix.

Reconfigure HyperTerm as its settings are causing the problem. When you run HyperTerm you should see "4800 8-N-1" at the bottom of the window, as shown in the red circle in the figure. If it instead says Auto-Detect you need to stop the session by clicking on the Disconnect button (circled in green) and goto the File menu, and Select properties. Click on configure. Ensure that the settings are correct and also make sure that you click the apply button. (If apply is greyed out, make a change then change it back then click apply). Now hit the Connect button and check to see if 4800 8-N-1 comes up.

RS232 Serial Line Protocol

The serial line protocol is a very simple means of electronic data transmission.  The first thing to realize is that, inside of that cable, a serial communications line is merely a small collection of wires driven by digital signals.  In the case of the serial protocol, the way in which these signals are driven is very simple: one bit at a time.  Both sender and receiver agree upon a line speed, and then – with the help of a couple control bits – the sender simply drives the serial line high (for a 1) or low (for a 0) a number of times at the proper speed.  The receiver samples the line at the previously determined speed and remembers the bit values that it sees.  In this way, full bytes can be reconstructed by the receiver and processed accordingly.

 

Even the details of RS232 are simple.  In the steady state, the line signal is simply held high.  When the sender wishes to begin sending a byte, it drives the line signal low for one “cycle” (the length of which is determined by the line speed, or “baud rate”).  It then simply begins driving the line either high or low, one bit of data at a time.  When a full 8 bits have been sent, the sender forces the line signal high to signify the end of the byte.  The process may then repeat (or the line signal may simply stay high for an indefinite amount of time). Note that it takes 10 bits to send 8 bits (one byte/character) of data: 1 bit to start the transmission and 1 bit to indicate the end, in addition to the 8 data bits.

 

 

Consider an example.  A PC wishes to send an ASCII character from its keyboard to your prototyping board.  Both your circuit and the PC are running at 4800 bits per second (bps).

 

  1. Sender holds line high indefinitely.
  2. Receiver waits for a “start bit” to signify the beginning of a byte transmission.
  3. The PC user presses ‘A’ (ASCII code 0x41 or 01000001 in binary).
  4. Sender forces the line low for one cycle (sends the start bit).
  5. Receiver prepares to receive the byte.
  6. Sender drives the line to a signal corresponding to the least significant bit (1).  It then sends five 0s, a 1, and then another 0.
  7. Receiver incrementally shifts each bit into an 8-bit shift register as it samples them.
  8. Sender has now sent all 8 bits, so it drives the line signal high (sends the stop bit).
  9. Sender resumes waiting for key press and driving line signal high.
  10. Receiver resumes waiting for a start bit (and presumably does something with its newfound byte).

 

Board Layout:

O1 - clock as always.
02 - each bit from the serial line.
03 - flag value "displayed".
LD7 - flag value "recieved".
LD6 - common reset.

module serial_control (clk,reset,charRcvd,received,displayed,newChar);

input clk,reset; //O1, LD6
input charRcvd; //the actual bit to begin shifted in O2
input received; //flag value that a new charRcvd exists LD7

output displayed; //flag value for FPGA to complete handshake O3
output newChar; //the new character

 

received

 

displayed

data

 

Your design does not need to worry about the transmission rate.  The FPGA will provide the serial data one bit per clock.  It will also allow the clock to be single-stepped as in the previous lab assignments.

 

Your “main controller” PAL will need to hold two, separate state machines: the one you already designed that controls the LCD, and a new one, the “serial controller”, that implements the receiving side of the RS232 serial line protocol as described.  The PAL which was previously only an 8-bit tri-state driver will now become the aforementioned 8-bit shift register and will be controlled by the serial controller. 

 

Warning! When making your tri-state shift register, you can not tri-state inside an always @ block. This is because your PAL is not robust enough to handle such logic. Instead tri-state outside the always block. The serial controller should monitor the serial data input for the start bit, and then shift the next 8 bits into the shift register, and finally assert the “write” signal to the LCD controller.  If you assert “write” on the stop bit, the LCD controller should be able to write the character to the LCD before another character starts to shift in, even if data is being sent at the maximum rate.  That is, there is no need to save the data while writing it to the LCD.

 

You should write the “serial controller” state machine as a separate Verilog file, and use a schematic to put the two state machines into a single PAL. You can then synthesize this schematic to make your PAL file.

 

You still need to tri-state the output of this shift register just like you did before, because you will still need to multiplex between its output and the output of your command decoder for the LCD.

Simulation

As always, you should get your design working in simulation before attempting to construct and test it.  We will provide a test fixture that provides the serial input that writes characters to the LCD. Make your own test schematic and import rs232_tf.v and lcd_tf.v (found on \\ntdfs\cs\cse\courses\cse370\04au\Labs\Lab8) and wire accordingly.

Completing the Assignment

After successful simulation of your design, program your PALs, and wire up the full circuit.  Be prepared to reprogram a chip for a bug fix, and wire accordingly.  In other words, try to wire as neatly as possible, and try to do so such that your chips may be extracted from the circuit without significant rewiring.

 

Full credit completion of this assignment will include all of the following by the given due date:

 

  1. Correct, working circuit checked off by a TA.
  2. Correct, complete state diagram for your main controller’s finite state machine.
  3. Printout of your Verilog for the shift register and main controller modules.

Extra Credit

Your design uses 3 PALs to implement the serial line to LCD circuit.  You should have room on your board for one more PAL, which you can use for extra credit.  Here are two ideas:

 

1.  Implement a string recognizer.  That is, implement a state machine in the 4th PAL that recognizes a (short) string, which causes the state machine to halt with the string displayed on the LCD.  You could recognize a regular expression or just a simple string. To test this circuit, a file will be printed to the serial output on the PC.

 

2.  Implement a decryption circuit. In this design, you will use the LFSR you designed in the lab to generate a random sequence determined at reset by the settings of the switches (the key).  Then, as each serial data bit is received, it is XOR’ed with one of the bits of the LFSR, and the LFSR advanced.  To test this circuit, you will need to encrypt the characters in a file and send them down from the PC.

 

Note: You do not have to do Extra Credit to earn a 4.0 in this class!!  Extra Credit will not make up for a poor showing on quizzes and the exam, although it can help offset missed or poor assignments.  Extra Credit is meant for those who like an extra challenge and have the time to spend on it.  You may do the Extra Credit as a project team.