CSE370 Laboratory Assignment 4

Using PALs (Programmable Array Logic)

Distributed: October 26 , 2004
Due end of lab session

Objectives

In this laboratory assignment you will learn to use PALs.  The PAL we will be using in this class is called the 22V10 (here is the functional logic diagram).  This is a very flexible PAL that you will be using in different ways this quarter. At the core of this PAL are 10 logic blocks that each computes a Boolean function. This output can either go straight to a pin or through a register to a pin. We are concerned only with combinational logic right now, so we will ignore the register. The output also feeds back into the PAL, so that you can use it to implement multi-level logic functions.

This is how this PAL gets its name: functions of up to 22 inputs, with 10 distinct outputs, hence, 22V10.  Note: for now, ignore the other logic elements in this PAL, we'll come back to them later in the quarter.  After you familiarize yourself with the component, you will write some Verilog code that will be compiled into the logic in this PAL. This is yet another useful capability of the ActiveHDL tool. We'll use the full-adder circuit from the previous lab assignment as the example.  You will then “program” the PAL and use it on your protoboard.

Tasks

  1. Before you come to lab, complete the Aldec Tutorial #3, which describes how to write simple Verilog modules and use them in schematics.
  2. As part of the tutorial, you will write and test the Verilog module for a full-adder. Create a test schematic and using the test fixture from Homework 3, make sure that your Verilog module works correctly.
  3. Spend some time familiarizing yourself with the 22V10 functional logic diagram.  Make sure you see how logic functions are computed in this component.
  4. Complete the entire PAL tutorial that explains how to compile a circuit into a PAL using ActiveHDL and the Cypress compiler. Now compile your full-adder Verilog module and then program it into a PAL using the PAL “programmer”. You should already have the Verilog file for this circuit and have verified it using the simulator. The PAL is the long chip with the image of a tree on it, and you should already have 2-3 of them in your kit.
  5. After you've programmed your PAL, place it in your circuit board and wire its inputs and outputs to some switches and LEDs, respectively. Verify that is operates correctly and show this to the TA.  In addition, you should make sure to review the reports generated by the compilation process and understand what equations were generated to be implemented by the PAL.  The TAs may ask you about this, so be sure to review it carefully.
  6. Now create a 4-bit adder using your Verilog full adder, and compile it for your PAL using Active-HDL. You can do this by placing 4 full adders in a schematic to create a 4-bit adder. Make sure you label the wires for the carries between the full adders, e.g. with C0, C1, C2.  After simulating to prove that it is correct, program the PAL. Make sure you select the right files and top level module in the synthesis options before you synthesize.
  7. You will find that the tools will not be able to compile this circuit to the PAL since it runs out of product terms. How many product terms does it need? How many product terms does the 22V10 have? This happens because the tools try to compile the functions into 2-level circuits, and this requires way too many product terms.
  8. To solve this problem, you will have to adjust the compiler options.  In the Tech Mapping tab of the Options menu, change the Node Cost from the default, which is 10, to 1.  This forces the compiler to be less aggressive about “flattening” your design into a 2-level implementation and, as a result, to keep the ripple-carry adder as the multi-level circuit that you want. After you compile your circuit into the PAL, test it using switches for input, and LEDs for output. Demonstrate that it works for the TAs.
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