//------------------------------------------------------------------------
// Title       : count8.v
// Description : This module implements simple counter with clear and enable.
//---------------------------------------------------------------------------

`timescale 1ns / 1ns

module count8 (clk, clr, enable, count);
   input clk, clr;	 // clr is like reset
   input enable;	// Enable counting
   output [7:0] count;  // Value of the the counter
   reg [7:0] count;
   
   // This block implements the counter register
   always @(posedge clk) begin
	  if (clr) count <= 0;
      else if (enable)  count <= count + 1;
   end

endmodule // count8