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CSE370 Assignment 5

### Distributed: 29 October 2004

Due: 5 November 2004

1. Using the attached 22V10
sheet, program the increment function for a 4-bit number. This
circuit has a 4-bit input D[3:0] and a 4-bit output Q[3:0], where Q = D
+ 1. Note that only part of the 22V10 is
given here. Use pins 2,3,4,5 for the
D[3:0] input and pins 22,21,20,19 for the Q[3:0] output, in that order.

2. In this assignment, you will implement and test a complete
16-bit carry-lookahead adder using Active-HDL. You will find test
fixtures for each of the components and the final circuit here: add1_tf.v, add4_tf.v,
add16_tf.v, cla4_tf.v.
Make sure you use only components from the lib370 library.

a) Design and test a 1-bit adder which has three
inputs, A, B, Cin, and three outputs, Sum, P, and G, where P and G are
the propagate and generate functions. You
may use either a schematic with gates, or a Verilog file like you wrote
for Lab#4.

b) Using your 1-bit adder, design and test a
4-bit adder component which has three input busses, A[3:0], B[3:0],
Cin[3:0] and three output busses, Sum[3:0], P[3:0] and G[3:0].
(This 4-bit adder is just four independent copies of the 1-bit
adder.)

c) Design and test a 4-bit carry-lookahead
component that has three inputs, P[3:0], G[3:0], Cin, and three
outputs, Cout[3:0], BlockP, and BlockG. BlockP and BlockG are the
block propagate and block generate functions. You may use either a
schematic with gates, or a Verilog file.

d) Using your 4-bit adder component and 4-bit
carry-lookahead component, design and test a 16-bit carry-lookahead
adder.

e) What is the size (# of gates) and delay of
your 16-bit carry-lookahead adder?

f) If you continued and made a 64-bit
carry-lookahead adder using these components, what would be the size
and delay of that circuit?

3. Complete the timing diagram below for the following circuit.
Assume that gates and inverters have a delay of 1ns, and that the
propagation delay of the register is 1ns. The vertical lines mark 1ns
time; thus, the clock cycle is 10ns.

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