CSE370 Tutorial 2 - Introduction to Verilog in Aldec Active-HDL 6.1


Module Reuse, Test Fixtures, and Verilog

Objectives

In this tutorial, you will learn the basics of hierarchial module design. That is, you will learn how to design modules which you may then use or replicate later in higher-level designs. The concept is much the same as a function in software, and it's a key CAD concept which will greatly aid your productivity in digital design.

First, you will download and attempt to understand a "test fixture" module written in Verilog. Second, you will connect the 1-bit full adder designed in the previous tutorial to a test fixture module. This text fixture will "exercise" the full adder circuit and verify that it works properly. Finally, you will learn how to write an alternate version of the full adder in Verilog, a hardware description language.

Even though this tutorial will show you all you need to know to create basic Verilog modules, you should experiment with Active-HDL on your own. You will find that there are many tools and options that have been left out of this tutorial for the sake of simplicity. By experimenting with these tools on your own, you will become more proficient with Active-HDL, and you may find different methods that better suit your style, while still achieving the same design goals.

Start Active-HDL

  1. Open Active-HDL.
  2. Select the “Open existing workspace” option and select your workspace from Tutorial #1 in the window, or click the “More…” button to attach and open it (Figure 1).

Figure 1

  1.  Click OK.

* If you have forgotten how to use the “More…” button refer back to Tutorial #1 for directions.

Test Fixtures

Test fixtures are used to automatically test and/or simulate design. A test fixture is usually written in Verilog to save time.

The operation of a test fixture is very simple. The outputs of your circuit become the inputs of the test fixture, and the inputs of your circuit are set ("driven") by the outputs of the test fixture. In this way, the fixture can stimulate your circuit and observe your circuit's corresponding output to verify its correctness. We are particularly interested in “self-checking” test fixtures that check the outputs and report an error to the console automatically. This reduces the headache of analyzing waveforms in complex circuits.

Note:  For this tutorial, the test fixture is provided for you.  In later assignments, you may have to write your own.  Make sure to take some time to read through and understand the Verilog code of the test fixture. It’s pretty easy to follow these examples to generate your own test fixtures.

The code provided will test a number of cases and print a series of messages to help you find errors within the circuit (if any!). These messages will be printed to the Console and a text file.

  1. You will need to add the following a file to your design: FA_tf.v (this test fixture tests a 1-bit full adder).  Download this file and place it in a folder you'll remember (e.g., on your Z: drive).
  2. Double-click “Add New File” in the Design Browser. Now, click the “Add Existing File” button.
  3. Navigate to the folder in which you saved the file, select FA_tf.v, click the “Make local copy” checkbox, and add the file (see the following figure).
  4. Notice that the file is now present in the design hierarchy in the Design Browser. We use the naming convention: <design name>_tf.v to name test fixtures so that it is easy to associate test fixtures with the components they test. If you choose different names for your full adder, make sure you rename these test fixtures by right-clicking the file in the Design Browser.


Figure 2

  1. Double-click the test fixture in the Design Browser to open this file in the main window.
  2. You do not need to understand the code completely, but read through the code and try to understand what it is doing and why it is doing it. Figure 3 shows some of the code for the full adder test fixture with key areas of interest circled in red. If you renamed the file, change the title and the module name to reflect this change.


Figure 3

  1. (Optional) This test fixture prints its results to a file as well as the Console by using the $fopen statement. You may change the name of the fixture's output text file by modifying the argument passed to the $fopen statement (see Figure 3). Once you have familiarized yourself with the code, save it and then compile it. As always, if you choose to modify this file, save the file after each modification, and recompile it afterward.

Block Symbols 

Active-HDL can create block symbols from your compiled schematic designs (and Verilog source code) in the Symbols Toolbox. We will create block symbols for the full adder you designed earlier and the full adder test fixture. This portion of the tutorial will walk you through placing a block symbol for the full adder into a new schematic and connecting it to a test fixture to ensure that it functions properly.

Note: These instructions assume that the full adder design from the previous tutorial is available in your current workspace. If it is not, you will need to add it manually. In this case, it is probably best to just create an empty block diagram in the current workspace for the full adder, copy/paste the old design into it, and compile.

  1. Add a new empty block diagram file called: <design name>_test. Do this by double-clicking “Add New File” in the Design Browser, select the “Block Diagram” option under the Empty Files tab, and enter the name in the “Name” field. Then, click OK. Remember to reset the design’s target HDL to Verilog.
  2. Open the Symbols Toolbox. Find the name of your design, and expand your design’s part list. You should see a “Units without symbols” list. Expand it and find the name of your full adder schematic. Select it, and notice that a block symbol appears in the bottom window of the Symbols Toolbox. Add this part to your schematic and notice that this component no longer appears in the “Units without symbols” list.
  3. Repeat step 2 to add the symbol for full adder test fixture to the schematic.
  4. You can edit block symbols by right clicking the part in the schematic and selecting the “Edit” option. (Note: if this option is not available, save, close, and reopen the file and try again.) While in edit mode, you can drag the pins to a new position within the symbol. Clicking outside of the part will end the edit session, and you will be prompted to save your changes.
  5. The test fixture will drive the input signals of the full adder and test the full adder’s outputs. Connect the two units using wires. The outputs of the test fixture connect to the corresponding inputs of the full adder, and the inputs of the test fixture connect to the corresponding outputs of the full adder (see Figure 4).

Figure 4

  1. Now that the units are connected, save, run the check diagram tool, and compile the test schematic.
  2. Set the test schematic as the top level, close any waveforms, initialize a simulation, and run the simulation for 80 ns. If you have forgotten how to do any of these steps, refer to Tutorial #1.
  3. The Console, along with a text file, will contain the results of the simulation. If all eight cases passed, end the simulation, and continue with the tutorial. If not, there may be some problems with your full adder (see Tutorial #1 for examples on how to debug your design).

A Bit of Wisdom: Always assume that you will make mistakes. Whenever you create a reasonably complex circuit, also create a test fixture for it. It may seem like a lot of work at first, but it will quickly pay off. As you make changes to your design, you need only re-run your test fixture in order to ensure that everything still works as expected.

Besides, manual waveform analysis is time consuming (as well as a suspected carcinogen). Imagine a more complicated design with several multi-bit signals. Explicitly setting stimulators for each bit (which is what you would have to do with a traditional waveform) is a real pain. Make your life easier, and get into the habit of test fixture creation now.

Creating a Verilog Module

Now we'll turn to creating a regular Verilog module.  It will implement exactly the same functionality as the full-adder schematic, but do so using Boolean expressions rather than gates.

  1. Add a new Verilog file to the design. To do this double-click on the “Add New File” in the Design Browser, then select the “Wizards” tab, and click on the “Verilog Source Code Wizard”. Then, click OK.



Figure 5

  1. In the New Source File Wizard, make sure that the box is checked next to the “Add the generated file to the design” option. Click the Next button.

  1. In the “Type the name of the source file to create” field, enter the name of your verilog file using a descriptive name. You must try to keep them distinct so as not to confuse both you and the tool.  Do not use the same name that you named your design or workspace. Also, do not fill in the name of the module; leave this field blank. Active-HDL will use the source files name for the module by default. This just makes it easier for everyone to keeps things straight.  Click the Next button (Figure 6).


Figure 6

  1. The next window that opens is where you add your input and output ports. These are the inputs and outputs of your module. To add ports, click the “New” button (see Figure 7). Choose whether you want an input or output port by clicking the desired radio button located under the “Port Direction” heading.  In the “Name” field, type the name of the port. We will only be using 1-bit ports, so ignore the “Array Indexes” fields for now. Your screen should look like Figure 7. If so, then click the Finish button.



Figure 7

  1. Aldec will open a Verilog file with the module, inputs, outputs, and wires already declared (see Figure 8). Locate the section of the file that contains the comment: ” // -- Enter your statements here -- //”.  In this area you will insert the code to give CO and S its value. The code should contain an assign statement along with the AND operator ( “&” ), OR operator (“|”), and the NOT operator (“~”). An example line of code where X, Y, Z are inputs and W is an output: assign W = ( Y & Z) | ( X & ~ Z);


Figure 8

  1. Save and compile your verilog module. As in tutorial #1, a green checkmark should appear in Design Browser next to your Verilog module if it successfully compiles and a red “x” will appear if problems occur.

  2. To verify your Verilog module follow the same procedure as above with the test fixture, but now substitute the schematic version of the full adder with your new Verilog module. First, Open the Symbols Toolbox and find the name of your design to expand your design’s part list. You should see a “Units without symbols” list. Expand it and find the name of your Verilog full adder. Select it, and notice that a block symbol appears in the bottom window of the Symbols Toolbox. Add this part to your test schematic by dragging the symbol from the bottom window. Notice that this component no longer appears in the “Units without symbols” list after it has been added to the schematic once. Now, simply disconnect the schematic-based full adder from the test fixture, and connect your new Verilog-based module. Test away.

Concluding Remarks

You should now have a sense for the usefulness and implementation of test fixtures and now know how to reuse simpler modules inside more complex, higher-level designs.  Although you did not explicitly do so in this tutorial, what would happen if you needed to use, e.g., four 1-bit adders in the same design? You would just instantiate your 1-bit adder module (as you did in this tutorial) 4 times, and wire them together appropriately. Simple, clean, and productive.

Continue to experiment with Active-HDL, and try to fully understand the Verilog code provided in this tutorial. Later in the course, you will use Verilog extensively to improve your digital design productivity. You will, of course, learn much more about it in the weeks to come.

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