CSE370 Tutorial 1 - Introduction to Aldec Active-HDL 6.1
Creating and Simulating Simple Schematics
This tutorial will introduce the tools and
necessary to design a basic schematic. The goal of this tutorial is to
familiarize you with Aldec Active-HDL and to help you
complete your assignment. After finishing
this tutorial you will know
- Start Active-HDL;
- Add and remove files to and from a design;
- Place parts in a schematic design from the course
- Use wires in a schematic design;
- Run a basic simulation; and
- Debug a schematic design.
Even though this tutorial will show you all you
need to know
to do basic designs and complete the assignment, you should experiment
Active-HDL on your own. You will find that there are many tools and
that have been left out of this tutorial for the sake of simplicity. By
experimenting with these tools on your own, you will become more
with Active-HDL, and you may find different methods that better suit
style, while still achieving the same design goals.
Additionally, you should visit the Active-HDL
Tips web page for help (it is linked from the Hardware
Lab’s homepage under “Help/Technical Tips/Aldec Active-HDL”). This
will be updated periodically with new hints and tips based on input
students and faculty who use the Active-HDL tools. We encourage you to
this web page and email any suggestions/tips of your own to the Hardware Lab manager or
First, start Active-HDL by
double-clicking the icon located on your desktop. If the icon is not
then go to Start and select “Active-HDL 6.1” under the Programs menu.
Create a new workspace
A workspace holds your designs, and
each design may consist of many files (i.e., schematics, Verilog source
etc.). When you open Active-HDL, you will be presented with the Getting
Before starting the steps below you
should create a folder to hold all of your Active-HDL work. Active-HDL
few levels of indirection thus descriptive naming is crucial if you do
to get lost in your own workspace and designs. Therefore, you should
general Active-HDL folder and ensure there are no spaces in the
directory path from here on out (i.e., “C:\My Documents\my design” is
instead use something like “C:\my_designs”). The reasons for excluding
in your directory path are to avoid errors in the synthesis
process. Even though this tutorial does not cover design synthesis, you
should get in
the practice of avoiding spaces in file names, workspace names,
component names, etc..
the License Configuration menu, select the “VERILOG Design Entry”
option in the
drop down list.
the “Create new workspace” option. This opens the New Workspace window (Figure 1).
a descriptive name into the “Type the workspace name:” field.
that every workspace creates a new folder within the specified
every new design creates a folder within your workspace folder. Without
naming convention, you will find yourself confused and wandering in a
the workspace directory by entering it in the “Select the location of
workspace folder:” field, or use the “Browse…” button to select the new
(we recommend you use your student drive).
the “Add New Design to Workspace” check box if it is not already
New Workspace window should look like Figure
2. If so, click the OK button, and continue.
Create a design
creating a workspace, the New Design Wizard walks you
through creating a design. A design can consist of one or more Verilog
schematics, and other design files. A workspace, as mentioned earlier,
contain one or more designs. You can add more designs later by
File/New/Design in the menu bar. Adding new designs this way is not
in our tutorials. Before attempting to add more designs beyond the
we will do shortly, you need to review the Active-HDL Tips
now, we will add the first design to the workspace by following the
provided on the following pages.
the “Create an empty design” option. Then click the Next button (Figure 3).
- Find the “Block Diagram Configuration:” field and select the
“Default HDL Language” option. Leave the “Synthesis tool:” field and
“Implementation tool:” field blank since we will not be synthesizing
New Design Wizard window should look like Figure
4. If so, then click the Next button.
the “Type the design name:” field, type a name for your new design. The
must contain only letters, numbers, and underscores (“_”), and cannot
with a number (i.e., 4bitadder is invalid, however, four_bit_adder is
Use descriptive names that do not match file names, other
or workspace names.
default, the design directory is under the workspace directory, and the
the default working library of the design is the same as the design
these default values alone. The reason for not modifying these values
because there is no need to do so and doing so may result in confusion.
window should now look like Figure
5. This is a good time to look at the directory path in the
location of the design folder:” field to ensure that there are no
anywhere in the directory path.
* Warning: the
directory path should not
- Double check your file name and location, then click the Next
- Make sure
that your design name is correct and the design directory is correct in
window that follows (not shown). If not, click the Back button to make
changes, or click the Finish button to create the design.
Once you have
created a workspace, it should appear in the field at the center of the
Started window the next time you start Active-HDL. Simply select your
workspace, and click the OK button to open it. If your workspace is not
in the Getting Started window, follow the steps below to locate and
“More…” button allows you to browse for existing workspaces (see Figure 1 on
the previous page). Click the “More…” to open the Workspace/Design
the “Attach And Open” button (Figure
for your workspace in the Open window (this is the window that popped
step 2), and select the file that is named <your workspace
the Open button.
not have to
create a new workspace for every new design (in fact, we strongly
doing so). However, you may find it convenient to have more than one
in order to organize and manage your designs. Regardless of how many
you create, Active-HDL will occasionally “forget” where these
located, especially as you move from one machine to another in the
Therefore, following the above steps will allow you to locate and open
previously created workspaces that do not appear in the Getting Started
Add a Block Diagram (schematic) file
this point your screen should look like Figure 7
(shown on the
following page). The frame on the left is called the Design Browser and
all of the components in your design. The frame on the bottom is the
and is where status and error messages are printed. If these frames are
open, or if you have closed them by accident, you can open them by
View in the menu bar. In the center of the screen is the main window
will draw your schematics.
your design is first opened, the Design Flow Manager
opens in this window. We will not be using this tool during this
the top of this window is the Standard toolbar. Finally, notice the tab
bottom left side of the main window. As you create schematics and other
components in your design, you can use the tabs at the bottom of this
make the corresponding file active in the main window.
- Double-click the “Add New File” option in the Design Browser (Figure 8). This will open the
Add New File window (Figure 9).
the Wizards tab in the Add New File window. Select the Block Diagram
icon, and then click the OK button (Figure
9). Note: If you add a Block
Diagram without using the wizard, you will need to reset the design’s
HDL (see the UW
CSE Active-HDL tips page online) before you can compile it;
your new schematic will be in italics in the design browser.
the New Source File Wizard, make sure that the box is checked next to
the generated file to the design” option. Click the Next button. Note: this window is not shown.
- Select the “Verilog” option, and click the Next button (Figure 10).
- In the “Type the name of the source file to create” field,
enter the name of your schematic design. Use descriptive names.
The tools will be using these names in a variety of ways. You
must try to keep them distinct so as not to confuse both you and the
tool. Do not
use the same name that you named your design or workspace. Also, do
not fill in the name of the module; leave this field blank.
use the source files name for the module by default. This just makes it
easier for everyone to keeps things straight. Click the Next
button (Figure 11).
- The next window that opens is where you add your input and output
ports. These are the inputs and outputs of your circuit. You
do not have to add any ports at this point in the design process;
adding the ports now will save time. If
you choose not to add any, click Finish and skip steps 7 through 9.
- To add ports, click the “New” button (see Figure
12). Choose whether you
want an input or output port by clicking the desired radio button
the “Port Direction” heading. There are also in-out ports that
are bi-directional, serving as both input and output. We won't be
using inout ports now but will come back to them later.
- In the “Name” field, type the name of the port.
- We will only be using 1-bit ports, so ignore the “Array
Indexes” fields for now. Your screen should look like Figure
12. If so, then click the Finish button.
wizard generates a schematic that is empty except for
any ports you specified in the design process (see Figure
13). Notice this schematic file has been
added to the design in the Design Browser on the left. Schematic files
Active-HDL are called Block Diagram files and have an extension of
question mark means the file has not been compiled yet, which we will
later. Also, new toolbars have been added below the standard tool bar,
are used to edit block diagrams.
At some point, you may wish to detach files from
design, or delete them completely. You can do any of those tasks by
right clicking the file in the Design Browser and selecting the
from the pop-up menu. You will then be asked if you want to detach the
(remove it from the design without deleting it completely) or delete
Obviously there is a lot more that you can and may want to do to manage
files, but for now just get comfortable with these basic steps in file
Place parts into your schematic
you are ready to build your gate logic. The steps below
will show you how to add basic gates to your schematic and how to add
input and output terminals, in case you decided not to do so in the
wizard process, or you realized that you are missing some terminals (Note:
this tutorial uses the icons in the toolbars and other shortcuts to
of the tools in Active-HDL; however, all the commands accessed from the
toolbars can be found in the menu as well). Additionally, you will need
how to move and delete gates to clean up your design’s appearance and
make it easy to read (especially for others).
14 is the final version of the schematic you will be
drawing. Your final design should look similar.
of the components you use may differ in appearance from the components
- You are required to use the components located in the standard
class library for CSE370. Do not use built-in symbols.
Therefore, you need to add
the symbols for the components in the standard class library to the
toolbox using the Library Manager. Open the Library Manager by clicking
Library Manger icon in the toolbar (Figure
the lib370 library in the left frame of the main window, and right
click it (Figure 16).
the “Add to Symbols Toolbox” option.
the Library Manger by clicking its icon in the toolbar, or select
the Symbols Toolbox by clicking the Symbols Toolbox icon in the toolbar
the plus symbol to the left of the “lib370” option (see Figure
17 above) to expand the list. Scroll down the
list to find the desired part from the list, or type in the name of the
the field at the top of the Symbols Toolbox to search the list.
on the parts name in the list and notice that its symbol appears at the
of the Symbols Toolbox.
the part to your schematic by dragging the symbol from the Symbols
- Active-HDL uses the standard Windows user-interface to select,
move, and copy items in the schematic (i.e., drag, Ctrl-drag for
multiple parts, Ctrl-z for undo, etc.). Figure
19 is an example of Ctrl-drag.
- (Skip steps 10 through 12 if you added all your input and output
terminals in the New
Block Diagram Wizard.) To add a terminal, click the drop down arrow
next to the
Terminal icon (Figure 20) in the toolbar (or click Diagram/Terminal in
the menu bar). Click
the “Input” or “Output” option in the expansion menu.
Click in the schematic where you want the
Notice that you can continue to click and add
multiple terminals. To stop adding terminals, press the Esc key. Note:
The Esc key is very useful to “get out” of just about any process
drawing wires, placing components, etc.).
Moving gates and terminals is as easy as clicking
the part to the new location. Additionally, the arrow keys are very
moving components precisely where you need them in the schematic. To
arrow keys, simply click once on the wire or part to be moved then use
arrow keys to reposition it. To delete parts, simply click the part to
deleted (when properly selected, the part will be outlined in a red
then press the Delete key. Try moving a gate around and see how
the wires connected to it move.
In addition to moving and deleting gates, you may
rotate and flip gates.
Typically, gates are drawn "left-to-right" (inputs coming from the
left, outputs going out to the right). There are exceptions to
this rule when the diagram can be made easier to read or much less
- Step 1: Select the part by clicking on it.
- Step 2: Right click on the part.
- Step 3: In the pop-up menu, select the “Mirror” or
Using wires in Active-HDL
This part of the tutorial will show you how to
connections using wires, how to move the wires, how to name wires, and
on the Wire icon in the toolbar (see Figure
- Now click anywhere in the schematic and drag your mouse to the
point in the schematic where you want the wire to end. Clicking on a
terminal will connect an end of the wire to that port or terminal,
another wire will create a junction, clicking on an empty space in the
schematic will create an anchor or bend in the wire at that point, and
double-clicking an empty space in the schematic will create an end to
at that point.
- When you are done placing wires, go back to select mode by
pressing the Esc key or clicking the Select Mode button in the toolbar.
- Select the wire by clicking on it (the selected wire will turn
red; Figure 22).
- Press the Delete key.
- Click and drag on the wire or part of the
wire to be moved.
- Drag your mouse to the new location and
release the button.
- Double-click the wire segment you wish to label. This opens
the Wire Properties window.
- In the “Segment:” field under the General tab, type the name (Figure 23).
Connections to terminals
made “by wire” or “by name”. “By wire” connections connect terminals by
drawing tham as connected in the diagram - their wires touch.
If a wire and a terminal have the same name, they are connected “by
name” and there is no wire connecting them in the drawing - but they
are connected because the signals have the same name. Lots
of intersecting wires can be confusing and named connections are used
to make easy to read
schematics. Figure 24 is
an example of both methods. Also, the final schematic version of the
presented earlier (Figure 14)
shows how to create an easy to read schematic using connections by
- Click OK.
* Complete your
it looks like Figure
Checking, saving, and compiling
At this point you should have a schematic with
terminals connected using wires. However, your file in the Design
still preceded by a question mark. Before you can run simulations you
compile your design, at which point the question mark will become a
mark if all is well, or a red “x” if there are errors.
- Always save your files first. Active-HDL, like most schematic
and simulation, or for that matter, just about any software, can and
will crash so save often. To do
this, click the Save icon in the toolbar, or press Ctrl-S with the
active in the main window. Remember to save early and often throughout
- Active-HDL provides a “Check Diagram” tool. This tool will
verify that the components are connected properly by printing the
the Design Rule Check report (DRC). To open this report, go to the
double-click the line that states, “Double click on this line to view
(see Figure 27 in the
DRC section). The DRC report is explained later in this tutorial.
the “Check Diagram” tool prior to compiling by clicking the
Diagram option in the menu bar (see Figure
- After you have checked your diagram and resolved any errors or
warnings, click the Compile icon in the Standard toolbar (Figure
26). See the DRC Report
(immediately following this section) and the debugging section, which
the Simulation section, for examples on how to locate and debug errors
design. The Console window will display the results of the compilation.
compiling a schematic, the console will generally compile successfully
there are gates and/or terminals that are not connected (in some cases,
warnings will be issued for unconnected ports). Therefore, just because
schematic compiles does not mean that it will do what you intended it
during simulations. This is the reason you need to check your diagram
compiling. Figure 26
shows a successful compilation even though there are terminals and
When you run the check diagram tool, a DRC report
created. Open this file by going to the DRC line in the Console and
double-click the appropriate line (see Figure
27 on the next page). This file will list any errors or warnings
design might contain, such as unconnected ports, mislabeled wires
terminals, and other connection-related errors/warnings. Each
the report is a hyperlink that will take you to the problematic
your design. Figure 27
shows an example of a DRC report file for a schematic with an error and
Simulating a design
that your design functions as you intend, you need
to simulate it. This portion of the tutorial will show you how to set
top-level, how to open a waveform, how to add signals to a waveform,
and how to
Close all open waveforms from previous simulations, if any, prior to
running a new simulation. Leaving waveforms from previous simulations
cause Active-HDL to not simulate or to do something other than what you
expect. The reason for this behavior is due to the fact that Active-HDL
that the signals in the waveform are the signals being used in the
top-level design. Multiple waveforms will confuse Active-HDL and cause
- Before you can simulate a design, you must set the top-level.
Since designs can be composed of multiple files or layers, we need to
Active-HDL which file is our top-level. After you compiled your block
file, two files were created: a Verilog file, and a module. Expand your
diagram file list by clicking the plus symbol next to the file name in
Design browser. Continue to expand the list until you see the module,
preceded by an “M” icon.
the following design entities are valid choices when setting the
configuration [“C” icon], a module [“M” icon], or an EDIF cell [“D”
- Right click the module.
- Select the “Set as Top-Level” option (Figure 28).
If you do not set the top-level,
Active-HDL will prompt you to do so when you attempt to initialize a
- Select “Initialize Simulation” under Simulation in the menu
bar (Figure 29).
After selecting “Initialize
Simulation,” notice in Figure 30
that the Structures tab is opened in the Design Browser.
- Click the New Waveform icon in the Standard toolbar (Figure 31).
- Click the file name in the top window in the Design Browser
under the Structures tab. Notice in Figure
32 how the signals and wires (Nets) appear in the bottom window
Design Browser (circled in red).
- Add the signals to the waveform by dragging the signals one by
one into the left side of the waveform. A faster method of adding
the waveform is to select the signals using the Shift or Ctrl keys. Now
drag them as described above into the waveform. You can also
right-click on a
selected signal, and click the Add to waveform option in the pop-up
shown in Figure 33.
- To simulate a design, we have to provide values for the input
signals. Active-HDL provides Stimulators to drive input signals in a
In the left half of the waveform window, right click on the input
wish to stimulate (see Figure 34
on the following page).
- Click the
“Stimulators” option in the pop-up menu (Figure
- The Stimulators window will pop up with the Signals tab
active. The large arrow points to a list of Stimulators, and your
shown on the left side of the window in the “Signals” field. The
shows the different stimulator options: choose the “Clock” option. See
Stimulators” at the end of this tutorial to learn about some of the
- With the Stimulators window still opened, you can set
additional signals by clicking the signals in the left side of the
Once you have added all three input signals (i.e., A, B, and CI),
clock period of 10 ns for A by entering the time in second box from the
the top of the window (see Figure
37). Click the Apply button.
- Select clocks with periods of 20 ns, and 40 ns for the other
- When you are finished applying your stimulators, click the
At this point, you are ready to run the simulation
waveform and stimulators.
- The “Run For” field located in the Standard toolbar controls
how long to run the simulation. You may change this by using the up and
arrows to the right of the field, or you may type in a time (Figure 38).
- Click the Run For button in the Standard toolbar (Figure
- To restart the simulation, click the Restart button in the
Standard toolbar (Figure 40).
Note: if you make changes to the waveform
stimulators or adding/removing signals, you need to restart the
Similarly, any changes in the file means the file needs to be saved and
recompiled prior to restarting the simulation. To end a simulation,
click Simulation/End Simulation in the menu bar.
is an example of a simulation using the steps provided in this tutorial.
Now that you have created a waveform and ran a
you should save that waveform. With the waveform tab active, press
save, or right-click the tab and select save (Figure
42). Remember to use descriptive names. A good naming convention
<design name>_wv. This is the naming convention that will be used
next assignment. For example, the waveform below would be saved as
You may have several waveforms for the same
design. This is
very useful in comparing different signal values and methods of driving
input signals. However, you should close all waveforms when you
to avoid confusing signals when simulating other designs (see the Important
note at the beginning of this section). You should experiment with the
different methods available and save the results in separate waveforms
comparison; however, this is optional.
Debugging a design
will walk through a simple, yet common, scenario with a
schematic that contains errors and warnings. Some of these problems can
pinpointed and solved by simply running a check diagram and reviewing
However, the DRC cannot find and report your logic errors. What do you
you have checked your design, compiled successfully, and when you run
simulation, your results are flawed? The techniques below will show you
use the tools provided by Active-HDL to trouble-shoot your design, and
of the most common mistakes. In the following steps we used
demonstrate the debugging process.
schematic was designed using parts from the Built-in library.
are no gate delays.
- First, we saved, and checked our design. When checking the
schematic shown in Figure 43,
Active-HDL generated the DRC report shown below in Figure
- Clicking on the first line took us to the broken connection on
the 3-input OR gate. The part in question was highlighted in a red box
shown here). Therefore, we simply reestablished the connection by
hanging wire to the 3-input OR gate port (shown fixed in Figure
- The second warning showed that net ‘C’ was without a source.
Again, we clicked this hyperlink, and it took us to our schematic and
highlighted the wire named ‘C’ in red (see Figure
45). The connection looked fine, but notice that we have no
the name of ‘C’. The terminal we wanted to connect from was ‘CI’. This
mistake is common when naming connections, and Active-HDL is good at
us to this mistake.
we had corrected the first two warnings, we clicked on the third. This
hyperlink took us to our schematic and highlighted the segment that was
earlier, but we had already fixed it in the second step. This could
there was another problem with this segment, or the problem was that
broken connection had raised two errors involving the two gates. At
we saved the file, and ran the check diagram tool again. Figure
shows the results of this DRC report, and according to Active-HDL, all
- We have now successfully compiled the design. We initialized a
simulation, added the signals to a waveform, provided clock stimulators
signals, and simulated the design. Figure
47 shows the results of this simulation. When comparing the
the expected results (we used a truth table), everything looked fine
got to the 10 to 15 ns period. The sum should have been 1 and the
should have been 0, but both were 1. This showed us that there was a
- With the simulation still initialized, we went back to our
schematic design by clicking the design’s tab at the bottom of the main
Alternatively, you can go back to any schematic design by
design’s name in the Design Browser.
- Then, we restarted the simulation. Since we were using clocks
of 10 ns, 20 ns, and 40 ns, we knew that the first problem arose at 10
Therefore, we entered 10 ns in the “Run For” field in the toolbar, and
simulation with the schematic open.
- The sum waveform showed that the sum was correct. Therefore,
we focused on the carryout logic. When running a simulation, there are
next to each input and output signal in the schematic that display
throughout the simulation. A green box means the signal is low (0), a
means the signal is high (1), a yellow box (z) means the signal is
and a blue box (x) means the signal is unknown. We noticed that after
the simulation for 10 ns that the box next to the carryout output
red (see Figure 48 on
the next page). Using the mouse-over feature, we traced the signal from
carryout terminal all the way back to the input signals.
- Since the carryout is determined by the 3-input OR gate, we
knew that the outputs of each of the AND gates and the OR gate should
0. As we mouse over each of the outputs, we notice a 1 at the output of
- Next, we needed to verify that the inputs were correct. By
rolling the mouse over the two inputs to the OR gate, we verified that
inputs were indeed correct. Since the signal ‘B’ was a 1 and the signal
a 0, the only way that we could have produced a 0 for the output was
AND gate. Therefore, our logic was flawed and we needed to change this
to an AND gate. As you can see, logic errors like this one are
Active-HDL, and you will need to use this technique or techniques of
to pinpoint these errors.
- We replaced the part by right-clicking it, and selecting the
“Replace Symbol” option and selected a 2-input AND gate from the pop-up
Then we connected the symbol, saved the file, ran check diagram, and
it while making sure to fix any new bugs we may have created while
This is a simplified example of what you may
your design process. However, the techniques described above can be
the same way to larger, more complicated designs. You need to know how
your designs using a simulation as well as the DRC report. Even if you
run into any problems with this assignment, you may need to use these
techniques in the more complex upcoming assignments.
This section will describe two of the available
that you may use in your simulations other than the Clock option you
The value option allows you to set a value of a
signal to 1, 0, z (high impedance), or x (unknown). For this tutorial
either 1 or 0 by following the steps below.
- With the Stimulators window open and a signal selected, click
the “Value” option in the list (see Figure
- Select the desired value from the “Force value” field (Figure 49).
- Click Apply, and repeat the steps above for other signals.
When you are finished, click the Close button.
- With the Stimulators window open and a signal selected, click
the “Formula” option in the list (see Figure
- In the “Enter formula” field, enter the value (1 or 0)
followed by a space and the time at which to assert this value. For
the following formula will cause a signal to start out at 1, then
change to 0
at 10 us and back to 1 at 20 us: 1 0 us, 0 10 us, 1 20 us (Figure 50).
- Alternatively, you can let Active-HDL create the formula for
you by entering the desired value and time offset in the fields
are allowed three sets of these values, then you can choose to repeat
sequence by entering a time in the “repeat above sequence every” field.
you have set your formula, click the Apply button.
- To set formulas for more signals simply add the signals and
repeat the above steps. When you are finished, click the Close button.
This completes the first tutorial for Active-HDL.
that this tutorial has only scratched the surface of the capabilities
program. We strongly recommend you practice using the techniques
within this tutorial while experimenting with and exploring other
techniques that Active-HDL offers. You may want to try the Verilog
that comes with Active-HDL as well. Don’t be discouraged if you do not
understand what all of the tools are used for or the concepts the
covers that have not yet been covered in class. By spending time with
and experimenting, you will save time by being better prepared for the
complicated upcoming assignments.
*Remember to visit the UW
CSE Active-HDL Tips web page
for hints and tips.
Comments to: firstname.lastname@example.org