CSE370 Laboratory Assignment 2
Constructing Simple Logic Circuits
Distributed: 13 October 2003
Due: 17 October 2003
Objectives
We will be using Aldec's Active-HDL 6.1 as our primary design tool this
quarter. In this laboratory assignment you will learn how to use the
tool to enter basic schematic diagram and simulate them. We will expect
you to use this tool to generate all the schematics
you'll be turning in as part of your written assignments (starting
with assignment #4). By the end of this lab you should know feel
comfortable you can enter a schematic for a design, set up simulation
stimuli, and verify that your circuit is correct.
Tasks
- Complete the entire introductory
tutorial
to the Aldec ActiveHDL 6.1 tool. You'll be asked to enter a
schematic for
the full adder circuit we discussed in class and in Chapter 2 of the
text. Make sure to complete the entire tutorial. It is
quite long but
very informative and thorough.
- Create a schematic drawing for the Fibonacci number circuit of
exercise 2.20 (the last problem on written assignment 2).
Make sure to minimize it first using K-maps. You should achieve a
sum-of-products expression with four terms (two with four literals and
two with three literals).
- Simulate your circuit for task 2 using the same technique as in
the tutorial. Create stimulators for the inputs A, B, C, and D
with D changing every 10 time units, C every 20, B every 40, and A
every 80. Make sure to run your simulation long enough so that
the inputs take on all possible combinations. Your simulation
results should clearly show that the output of the function is only
true when the inputs correspond to a Fibonacci number (1, 2, 3, 5, 8,
or 13). Show the result of the simulation to a TA and have them
check you off as having completed this laboratory assignment. They may
ask you to show them your work and explain your circuit.
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