Given the state diagram below, synthesize a sequential logic circuit that exhibits the behavior specified. Call the input A and the single output Z. Also, show pseudo-Verilog code (clearly identifying any assign or always blocks) that specifies the same behavior. Implement the state transitions using an always block and the output using an assign statement.

The state transition table for the state diagram is:

The equations for the next-state and the output are:

Z = Q1' Q2'
D1 = A
D2 = Q1'

Note that states 10 and 11 are equivalent.  However, combining them would lead to more complex equations.

The circuit corresponding to these equations is:

The Verilog for this state machine (note use of symbolic states and case statement) is:

module state_machine (A, Z);


	input A;

	output Z;


	reg [1:2] state;


	parameter S0 = 2'b00;

	parameter S1 = 2'b01;

	parameter S2 = 2'b10;

	parameter S3 = 2'b11;


	assign Z = (state == S0);


	always @(posedge clk) begin

		case (state)

			S0: if (A) state <= S3; else state <= S1;

			S1: if (A) state <= S3; else state <= S1;

			S2: if (A) state <= S2; else state <= S0;

			S3: if (A) state <= S2; else state <= S0;

		endcase

	end


endmodule

The Verilog for the circuit derived above is quite different:

module state_machine (A, Z);


	input A;

	output Z;


	reg [1:2] state;


	assign Z = (state == 2'b00);


	always @(posedge clk) begin

		state[1] <= A;

		state[2] <= ~state[1];
	end

endmodule

Although this is more compact, it is more difficult to change if the state diagram changes. Note that it is important to use non-blocking assignments (<=) in the always block. If they were blocking assignments, the value of A would affect both flip-flops every cycle.