Implement the function Z = A'B'C'D + A'B'C + A'B + A + BD + B using the PLA provided below.

As provided, the function has one too many terms for the PLA provided. Best to start with a K-map of the function so that we can easily identify any redundant terms. It turns out the function can be simplified to Z = A + B + C + D which has only four terms leaving one extra in the PLA. However, many other solutions are correct. It should have been relatively straightforward to see that BD is redundant given that B is a term.

We can rewrite Z into a form similar to the 8:1 multiplexer equation:

Z = A'B'C'I₀ + A'B'CI₁ + A'BC'I₂ + A'BCI₃ + AB'C'I₄ + AB'CI₅ + ABC'I₆ + ABCI₇

Z = A + B + C + D
Z = (A'B'C'D')'
Z = A’B’C’(D) + A’B’C(1) + A’BC’(1) + A’BC(1) + AB’C’(1) + AB’C(1) + ABC’(1) + ABC(1)

The parentheses indicate the values to assign to the corresponding inputs of the multiplexer. This lets us easily complete the multiplexer design by assigning values of D to the first input and 1 to all the others.

Extra credit: Implement the function yet again using the 3:8 decoder provided below and as few extra gates as possible.
 

The decoder is used to form all the product terms of the inputs A, B, and C. Recall that the input to the decoder is an enable signal that is ANDed with every one of the minterms. If the enable input is 0, all the outputs are 0. We can use the enable input to inject D into the output equations. By setting the enable input to D' we form the A'B'C'D' term at the first output. This is just the complement of our function, Z. Two inverters do the job.

If we don't use the enable input, then we can form Z with the help of an inverter and a NAND gate that forms (A'B'C'D')'.

Yet a third solution, uses a large fan-in OR gate to group all the output of the decoder (which corresponds to A + B + C) and then ORs in D as well. A variant of this is to OR all the outputs of the decoder but AND the A'B'C' output with D first.