CSE370 Assignment 9

Distributed: 26 November 2003
Due: 10 December 2003


  1. Katz/Borriello, Contemporary Logic Design, Chapter 8
  2. Katz/Borriello, Contemporary Logic Design, Chapter 10 (especially, section 10.6, skip section 10.4)


NOTE: You can work with your laboratory partner on this assignment. You will turn in a single copy of this written assignment with both of your names on it.

See design project description.

  1. Complete the design of the modules left for you to design in laboratory assignment #8. Turn in a state diagram for the MainController and the Verilog code for both the MainController and InitDecoder modules.
  2. Discuss how you came up with your state assingment for the MainController. Is your encoding one-hot, output-oriented, sequential, etc.? Why?
  3. Simulate your complete design including the test fixtures provided. Turn in simulation waveforms that clearly show a complete character processing cycle (from character being sent serially by Sender to the command to print it arriving at the display (RS/RW/DB/E) ). Make sure to include all signals of interest in the simulation waveforms.
  4. Do you see any problems with your solution if two consecutive characters arrive very close together? If so, what will be the manifestations of this problem? If not, why not?
  5. EXTRA CREDIT: repeat exercises 1, 2, and 3 above when including special commands to the display in the data from the PC. For example, you can select an ASCII code to be a clear command. Your circuit will have to issue special commands to the display to get this to happen. If you feel ambitious, add a backspace command. 10% extra credit for clear, 20% more for backspace. Therefore, a total of 30% extra credit but you have to actually implement these functions in the PALs and demo them in lab.


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