// Verilog Description of a 4-bit shift register
// Inputs: HOLD, LOAD, CLR, COMPL(two's complement of contents)
// Author: Steven Balensiefer
// Date  : 11/18/03

module comp_reg(CLK,LOAD,HOLD,CLR,COMPL,D_IN,D_OUT);
   // Inputs:
   input CLK;
   wire  CLK;
   input HOLD;
   wire  HOLD;
   input LOAD;
   wire  LOAD;
   input CLR;
   wire  CLR;
   input COMPL;
   wire  COMPL;

   input [3:0] D_IN;
   wire [3:0]  D_IN;
   // Outputs:
   output [3:0] D_OUT;
   reg [3:0] 	D_OUT;
   
   // Main logic
   always@(posedge CLK) begin
      if(CLR == 1'b1) begin
	D_OUT <= 4'h0;  // clear all bits by assigning 0.
      end else if (LOAD == 1'b1) begin
	D_OUT <= D_IN;
      end else if (COMPL == 1'b1) begin
	D_OUT <= -D_IN; // return the 2s complement
      end else if (HOLD == 1'b1) begin
	D_OUT <= D_OUT;
      end
   end
endmodule // comp_reg