CSE370 Assignment 7

Distributed: 10 November 2003
Due: 17 November 2003

Reading:

1. Katz/Borriello, Contemporary Logic Design, Chapter 7
   

Exercises:

1. Write a behavioral Verilog module for the circuit of exercise 5 in the previous assignment and simulate it for the same conditions. Turn in the Verilog code and the simulation waveforms.
2. CLD-II, Chapter 7, problem 7.3.
3. CLD-II, Chapter 7, problem 7.9.
4. CLD-II, Chapter 7, problem 7.11.
5. CLD-II, Chapter 7, problem 7.12.
6. CLD-II, Chapter 7, problem 7.15.

Rationale:

• To begin understanding the basic sequential logic building blocks: registers, counters, and simple state machines.
• To learn the use of simulation tools and hardware description languages for sequential circuit blocks.