CSE370 (Autumn 03) Assignment 6 Solution
1. CLD-II, Chapter 5, Problem 5.15
Design a 4-bit circuit that can perform either BCD or binary addition under control of a modes setting M.
If M=1 the outputs are BCD addition, and if M=0 the outputs are binary addition.
2. CLD-II,
Chapter 6, problem 6.1
6.1 Build a feedback circuit with cross-coupled NAND gates. What input conditions cause the state of
this latch-like device to be reset? To be set? Does this circuit have forbidden inputs? If so, what are they?
|
|
3. CLD-II, Chapter 6, problem 6.2
6.2 Design a circuit with three inputs and three outputs that determines which of the inputs is asserted first.
The circuit will produce a logic 1 on the output that corresponds to that input. Discuss how you would
expand this circuit to a larger number of inputs, say 12 inputs or 30 inputs.
|
|
|
|
|
|
Extending any of these solutions to 12 or 30 inputs would require 12 or 30 input gates which would have a
significant delay. It might be possible to use a tree of gates, but the delay involved would still be notable.
4. Chapter 6, Problem 10
6.10 Given the input and clock transitions, indicate the output of a D device assuming:
a. It is a negative edge-triggered flip-flop.
b. It is a master/slave flip-flop.
c. It is a positive edge-triggered flip-flop.
d. It is a clocked latch. You may assume 0 setup, hold, and propagation times
5. CLD-II, Chapter 6, problem 6.28,
6.28 draw a schematic of this basic register block using ActiveHDL and simulate it for the case where you
load the value "0011", hold the contents of the register for 2 clock cycles, then clear the register, then load
a new value of "1100", hold this new value for 1 cycle, and, finally, replace it with its 2s complement.
Ignore the last sentence of the problem statement given in the text. In any cycle, you can assume that one
and only one of the four control signals (HOLD, CLEAR, LOAD, and COMPLEMENT) will be asserted.
Turn in the schematic drawing and the simulation waveforms.
(One of many possible ways to implement)
This design assumes that the
complemented register values will only exist while the complement
signal is high. Making a small change would
cause the complemented register values to replace
the register’s contents. Simply
moving the feedback after the XOR gate would accomplish this
change. In that case, leaving COMPL
high for more than 1 cycle would cause the output
to oscillate.