CSE370 Assignment 6
Distributed: 31 October 2003
Due: 10 November 2003
- Katz/Borriello, Contemporary Logic Design, Chapter 6
- CLD-II, Chapter 5, problem 5.15.
- CLD-II, Chapter 6, problem 6.1.
- CLD-II, Chapter 6, problem 6.2, don't worry about the type of
switch, just use digital inputs and assume that the inputs all go high
and stay high at different times, your circuit should have as many
outputs as inputs with only one ever going high, namely, the output
corresponding to the first input to go high. Explain why this is
a sequential circuit?
- CLD-II, Chapter 6, problem 6.10 (use template).
- CLD-II, Chapter 6, problem 6.28, draw a schematic of this basic
register block using ActiveHDL and simulate it for the case where you
load the value "0011", hold the contents of the register for 2 clock
cycles, then clear the register, then load a new value of "1100", hold
this new value for 1 cycle, and, finally, replace it with its 2s
complement. Ignore the last sentence of the problem statement
given in the text. In any cycle, you can assume that one and only
one of the four control signals (HOLD, CLEAR, LOAD, and COMPLEMENT)
will be asserted. Turn in the schematic drawing and the simulation waveforms.
- To begin understanding the basic building blocks of sequential
- To learn the use of simulation tools and hardware description
languages for sequential circuit blocks.
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