CSE370 Assignment 5

Distributed: 27 October 2003
Due: 3 November 2003


  1. Katz/Borriello, Contemporary Logic Design, Chapter 5


  1. CLD-II, Chapter 4, problem 4.20.
  2. CLD-II, Chapter 4, problem 4.28.
  3. CLD-II, Chapter 5, problem 5.2.
  4. Construct a 4-bit ripple-carry adder with four full-adder blocks using Aldec ActiveHDL. First construct - out of basic gates from the lib370 library - a single-bit full-adder block to reuse. Verify your design using simulation, turn in the schematic and timing waveforms showing what happens when you have "1111" and "0000" as the numbers to be added and you change the "0000" to "0001". How long does it take the sum to get to the right value? Repeat this experiment starting with "1010" and "0000" and changing the "0000" to "0101".  Explain the differences between the two cases.
  5. Repeat the previous problem but now construct a 4-bit carry-lookahead instead.  Use the same full-adder module as the previous problem. Repeat the two simulations.  How much faster is the carry-lookahead adder in both cases? Explain the differences with the result of the previous problem.  How do your circuits from this problem and the previous one compare in the total number of gates they use (remember to consider gates in all sub-blocks)?
  6. Design a 8-bit carry-select adder for unsigned numbers. It should be designed hierarchically at the schematic diagram level and include 3 instances of the 4-bit ripple-carry adder module you created in the previous problem. You'll also need to include some multiplexers. Make sure that your 8-bit carry-select adder also has a carry-out in case anyone would ever want to use it to build a larger adder. Verify its operation for "11111111" + "00000001". Turn in the schematic and simulation waveform.


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