CSE370 Assignment 4

Distributed: 20 October 2003
Due: 27 October 2003

Reading:

1. Katz/Borriello, Contemporary Logic Design, Chapter 4 (skip material on FPGAs)
   

Exercises:

1. CLD-II, Chapter 3, problem 3.24, parts a, and b (the switch goes from bring closed to being open).
2. CLD-II, Chapter 4, problem 4.2 (use the equation f = ABCD' + AB'D + B'D' + BCD' + BDE instead of the one given in the chapter 4 handout).
3. CLD-II, Chapter 4, problem 4.7 (use the chips in your lab kit for part b).
4. CLD-II, Chapter 4, problem 4.8 (use this template).
5. CLD-II, Chapter 4, problem 4.10 (for part c, disregard the hint provided and use this one instead: HINT: Please use A and C to control the 4:1 multiplexer and use one *XOR* gate on an input of the multiplexer, assume B and D are available in complemented or uncomplemented form.)
6. CLD-II, Chapter 4, problem 4.17, parts a, b, c, and d.

Rationale:

• To practice realizing combinational logic using regular logic structures.
• To begin to understand the process of mapping logic to programmable logic devices.