CSE370 Assignment 4
Distributed: 20 October 2003
Due: 27 October 2003
Reading:
 Katz/Borriello, Contemporary Logic Design, Chapter 4 (skip
material on FPGAs)
Exercises:
 CLDII, Chapter 3, problem 3.24, parts a, and b (the switch goes from bring closed to being open).
 CLDII, Chapter 4, problem 4.2 (use the equation f = ABCD' + AB'D + B'D' + BCD' + BDE instead of the one given in the chapter 4 handout).
 CLDII, Chapter 4, problem 4.7 (use the chips in your lab kit for part b).
 CLDII, Chapter 4, problem 4.8 (use this template).
 CLDII, Chapter 4, problem 4.10 (for part c, disregard the hint provided and use this one instead: HINT: Please use A and C to control the 4:1 multiplexer and use one *XOR* gate on an input of the multiplexer, assume B and D are available in complemented or uncomplemented form.)
 CLDII, Chapter 4, problem 4.17, parts a, b, c, and d.
Rationale:

To practice realizing combinational logic using regular logic
structures.
 To begin to understand the process of mapping logic to
programmable logic devices.
Comments to: cse370webmaster@cs.washington.edu
(Last Update: 10/15/03)