| Week | Monday | Wednesday | Friday | |||
|---|---|---|---|---|---|---|
| 1 | 4/01 | Introduction
Course overview The digital age |
4/03 | Binary numbers
Number systems Binary codes |
4/05 | Boolean algebra |
| 2 | 4/08 | Basic electronics
Logic gates |
4/10 | de Morgan's Theorem
Canonical forms |
4/12 | Boolean cubes
Kmaps Assignment 1 due |
| 3 | 4/15 | Kmap examples
Multilevel logic |
4/17 | Design examples
AOI gates Timing diagrams |
4/19 | NAND & NOR gates
Assignment 2 due Quiz #1 |
| 4 | 4/22 | HDLs
Combinational Verilog |
4/24 | Multiplexers
Demultiplexers |
4/26 | PLDs: PLAs, PALs, PROMs
Assignment 3 due |
| 5 | 4/29 | ROMs | 5/01 | Adders
ALUs |
5/03 | Hazards
Combinational-logic summary Assignment 4 due Quiz #2 |
| 6 | 5/06 | Sequential-logic overview
FSM example: Combination lock |
5/08 | Latches
State diagrams Clock |
5/10 | Flip-flops & registers
Metastability Assignment 5 due |
| 7 | 5/13 | Cascading flip-flops
Clock skew Counters |
5/15 | Counter design
Self-starting counters |
5/17 | Sequential Verilog
RTL & logic synthesis Assignment 6 due Quiz #3 |
| 8 | 5/20 | Counter design examples
Finite-state machines |
5/22 | Moore & Mealy FSMs
State assignment |
5/24 | Separating datapath & control
FSM example: Ant brain Assignment 7 due |
| 9 | 5/27 | Memorial Day Holiday | 5/29 | Retiming
FSM example: Vending machine |
5/31 | Optimizing FSMs
One-hot encoding CPLDs Tristate buses |
| 10 | 6/3 | Switch debouncing
Asynchronous circuits Assignment 8 due Quiz #4 |
6/05 | Computer organization | 6/07 | Transistors |
| 11 | 6/10 | Makeup quiz: 2:30 p.m. | ||||