Homework Set 9
DUE: Wednesday Dec. 11 , 2002, Start of class
Unless otherwise noted, you may collaborate with other CSE370 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.
Late Homework Policy:
The weekly assignments are due at the beginning of class. Assignments handed in during or immediately after class will incur a 10% penalty. Your assignment will be penalized 10% per day for each additional day late. Assignments due Friday will be charged 20% if turned in over the weekend, 30% if turned in on Monday, etc.
In this assignment, you will replace some of the components in the processor design with components that you will design using Verilog. Make a copy of your processor Model 2, which implements branch instructions, and modify it as described below. Replace each of the following modules with new modules designed using Verilog. Show that your modules work correctly by executing the test program that we will give you. You might want to change one module at a time so that if you have bugs, you'll know which module is at fault.
1. (50 points) Replace the cla4 module in the ALU with a verilog module that uses only continuous assignments to describe the functions computed by cla4. Call your new component "cla4ver.v"
2. (50 points) In the register file, replace your implementation of the multiplexors with a Verilog implementation of a multiplexor using an always block. Call your mux "mux4_1_16ver.v" (or "mux8_1_16ver.v").
3. (50 points) In the register file, replace the 16-bit register module with a Verilog module. Call this register "reg16ver.v"
You should turn in a printout of the Verilog modules you wrote, a copy
of the schematics you changed showing the new modules, and a screen shot that
shows that the test program works correctly. The screen shot should
show the contents of the register file.